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Dear, Sir.
My customer is considering CD74HCT4067-Q1 as the Demux function.
They are asking the data latch(data holding) will be performed on each output,
i0 to i15.
I believe the schematic on the datasheet will be the latch circuit, but symbol
is not clear.
So, I would like to double-confirm this device has the data latch(data holding)
will be performed on each output.
Sorry to ask this kind of matter. Hoping to get your advice.
Best Regards,
H. Sakai
Hideyuki,
The P/N in the diagram is supposed to represent a transmission gate switch (bilateral switch) which is a type of switch that has an NFET in parallel with a PFET. This switch architecture will support rail to rail operation and have a flat on-state resistance curve vs input voltage vs a single NFET switch which will clamp the input voltage at it approaches Vcc.
1) Yes, PN block is working as a switch
2) Correct, the S0-S3 are control logic pins that determine which switch path will be on while the others "off" paths will be high impedance.
Thank you,
Adam
