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TMUX1111: Leakage under powered off condition

Part Number: TMUX1111
Other Parts Discussed in Thread: TMUX1511

The question below is a cut / paste from a field person

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We wanted some clarifications around TMUX1111 with respect to leakage currents under powered off condition.

Below is the schematic implementation in our circuit.

Help us with your responses for below

 

  1. With VDD supply at off condition and SEL pins at floating, can the above FET SW isolate D from S lines ?

In the above scenario we will have SPI activity at 1.8V level on D lines, which needs to be isolated on S side.

 

  1. With VDD supply at off condition and only SEL lines pulled high, will the FET SW isolate D from S lines ?

 

  1. Is the above condition recommended for operation ?

 

  1. In one of the articles we came across powered-off protection feature on TMUX1511 FET SW. can this provide isolation in the VDD unpowered condition, as per our requirement ?

 

  1. Though TMUX1111 datasheet does not specify about  powered-off protection, is this feature supported on TMUX1111  as  they both are from same family?

 

  1. Is there any drop-in replacement chip for  TMUX1111 with above feature ?

  • HI Robert,

    For Questions 1 - 3 and 5:

    The TMUX1111 has an Absolute Maximum Voltage Rating of VDD + 0.5V, so the device is not only not guaranteed to isolate signals between the S and D pins, but runs the risk of unexpected part behavior as well as possibly damaging the part. It is not recommended to operate the part this way.

    For Question 4:

    Powered Off Protection, as used in the TMUX1511, would work for your described scenario.

    For Question 6:

    Unfortunately there is not a direct drop in replacement for the TMUX1111 that would include Powered Off Protection. The TMUX1511 would be the closest part that meets this need. The TMUX1511 is available in the the same UQFN package, but the pin out is different. 

    Best Regards,

    Parker Dodson