TMUX136: Support MIPI-DSI

Hey Ali,
Does your design need differential lanes? 
If not, this would be do-able with the TMUX136 but would require atleast 2 devices. The clocks could be directly connected to the MIPI modules from the processor but if you wanted to switch the clocks too, it would require another (3rd) chip. *Pic below to clarify better. There would be some difficulties in actually designing this from the perspective of wires crossing and the added digital logic lines may require some extra layers in board design though. However, if you require differential lanes, then the TMUX136 would not be appropriate. TS5MP646 would be your best bet for differential. However, seeing as how it isn't suitable for you layout constraints, if you could relay your concerns with it, depending on the constraints I can try and help find a work-around or offer another solution.


Thanks!
Rami Mooti

Dear Rami,

Thanks for your support.

We need differential lanes. So, i think i 'll try to find another mipi switch.

If I use TS5MP646, layout will be special-product with new constraints and getting cost-high.

For example; it will be min clearence 40um, min.line width aprox. 50um , via size 35umx15um like that...

I wish there is QFN or alternative similar package.

Thanks.

Ali

Dear Sami,

It looks much better. Thanks a lot for your support.

I've a few questions about it;

1) I've 4Data+1Clk in diff. (forgot to say before. Sorry for it.) Can I use AUX (SDA/SCL) channel for MIPI clock path or data path? Does it act as normal diff. signal line? (like DA/DB).

2) If I can use AUX channel for clock/data lines, there will be no pull-up or pull-down resistor on AUX+- lines. That is negative effect to work?

3) I see HD3SS215I (QFN), what about do you think? Is it suitable MIPI 4Data+1Clk ? Its AUX ch. seen as diff line in datasheet. But, AUX ch. bandwidth (typ.720MHz) may not be sufficient for our resolution. Right?

Regards.

Ali