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TS3L4892: TS3L4892

user3551156
Prodigy 30 points
Part Number: TS3L4892

I'm estmating a Gigabit ethernet  swith item  with TS3L4892. It seems simple,but really not . I don't know why I can't swith the ethernet by manual .Following is my schedule .

After power on ,the SEL signal is pulled up by a  resister. so An=nB2, then I change SEL signal by manual to low level, An should nB1,

But there is signal on the output .

Is there problem on my design ?

Thanks

  • 0
    TI__Expert 5660 points

    Hello, and welcome to the E2E forum!

    Could you help me understand more about the signal that you are seeing at the output? What voltage is the signal? Do you have a scope shot or measurement to share?

    Thanks,
    Kate

  • 0 in reply to Kate Dickson
    Prodigy 30 points

    Hi Kate, thanks very much for your reply.

    I have solved my problem.The chip TS3L4892 doesn't be solered  well. QFN is hard by manual.

  • 0 in reply to user3551156
    Prodigy 30 points

    Hi Kate,Another questions appears. the  data speed down to 15MB/s when pass through TS3L4892. But if I connect two laptops directly by a net wire, the data speed is about 110MB/s. I don't know what happens to my board. How can I solve it?

  • 0 in reply to user3551156
    TI__Expert 5660 points

    Hello,

    Thanks for the follow-up. Did you fix the soldering issue on your board and confirm the switch is functioning?

    For high-speed applications, it's very important to follow recommended board layout guidelines:

    • TI recommends keeping the high-speed signals as short as possible.
    • Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended.
    • When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
    • Do not route traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals. • Avoid stubs on the high-speed signals because they cause signal reflections. If a stub is unavoidable, then the stub must be less than 200 mm.
    • Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing over anti-etch, commonly found with plane splits.
    • Due to high-frequency signals, a printed-circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer.
    • The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.

    Best regards,
    Kate