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SN74CBTLV16292: S_Parameter_Model

Part Number: SN74CBTLV16292
Other Parts Discussed in Thread: TS3DDR3812

Hi,

I would like to get an S-parameter model for SN74CBTLV16292. I need this to combine with board interconnect in a system-level S-parameter analysis.

thanks,

-Shriram 

  • Hi Shriram,

    We unfortunately do not have this devices S-Parameter Model Available. 

    Best,

    Parker Dodson

  • Ok. Do you have a standalone SPICE model for this component?

    thanks,

    -Shriram

  • Hi Shriram,

    We have a HSPICE file located here: https://www.ti.com/product/SN74CBTLV16292   

    If you can't run an HSPICE file we do have an alternative. We don't have a SPICE model  and due to the age of the part I am not sure when/if a model would be available.- but to simulate channel performance on the signal a simplified model can be used. Please see below:

    The channel of a mux is modeled as above. You then put in the Ron closest to your application (or the range if you are doing a parametric sweep) The capacitors are the I/O caps - they are connected to ground. Adding additional time controlled switches can help model the basics of switching in the device as well. 

    If you have other questions please let me know!

    Best,

    Parker Dodson

  • Thanks for the information. I will include this in my simulations and update accordingly if I see any issues.

    How would the impedance for this mux compare with that of the TS3DDR3812 design?

    regards,

    -Shriram

  • Hi Shriram,

    The impedance variance will depend on frequency - the TS3DDR3812 has lower parasitic capacitances so they will be high impedance for a larger frequency range than the  SN74CBTLV16292 which has a slightly higher on capacitance. They will perform similarly at low frequencies but there will be more signal attenuation across the device due to high frequency signals that cause the parasitic capacitances to approach lower impedances - there shouldn't be a huge difference as both of the capacitances are lower - but the TS3DDR3812 is most likely going to provide the lowest signal attenuation in most cases.

    If you want to include package details in the simulation - the IBIS model provides the package parameters for a few of the packages. The ranges of the pins can be found below with the package name noted in the top:

    You can add these to the simulation results to include general package parameters. The packages for the SN device are a bit worse than the TS3 device. For information on how to include the package parameters in the sim profile you can refer back to the E2E post where I included the general model + package parasitics. For more exact measurements for the pins you can also find it within the IBIS model on the product page.

    Please let me know if I can help you with anything else!

    Best,

    Parker Dodson

  • Hi Parker,

    Appreciate the information and details. I checked the BOM and the part selected for our board design is SN74CBTLV16292GR. Do you have the package parasitics for that specific one? If not, which of the ones you listed would provide the closest approximation?

    thanks,

    -Shriram

  • Hi Shriram -

    I apologize - it seems the package code and the Orderable part numbers don't align great. The GR version of the part is the DGG (TSSOP) package - so you can use the parameters labeled DGG

    Best,

    Parker Dodson

  • Hi Parker,

    Thanks very much! Appreciate your help. I am running some analysis comparing the two components and will share some data with you.

    We can close this thread.

    regards,

    -Shriram