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Original question:

TS5MP646: (TMUX646 Pin-to-pin upgrade supporting 6-GHz bandwidth available) Recommended products

TS5MP646: (TMUX646 Pin-to-pin upgrade supporting 6-GHz bandwidth available) Daisy chaining for 1:3

Charles Oladimeji
Mastermind 33805 points
Part Number: TMUX646TS5MP646
Other Parts Discussed in Thread: TS5MP646

Hi,

We plan on using this switch to route CSI2 lanes with 600 Mbps max speed. We need to route from 1 IC to 3 headers so we are considering daisy chaining with the 4th output unused.

  1. Is daisy chaining this switch recommended
  2. What are the downsides? Any study on this?
  3. Any special termination recommendation for the unused lanes or its okay to leave it floating?
  4. is there a 1:3 MIPI switch alternative that can be used to avoid the daisy chain?

Regards,

Charles O 

  • 0
    TI__Guru 52352 points

    Hi Charles,

    A few  quick clarification questions:

    1. Do all the headers need to be be connected to the IC at the Same Time and want an binary connected/non-connected net or Do you just want to switch between which jumper has access to the lanes.

    2. How Many Lanes are You routing ? 

    Daisy Chaining Risks

    With Daisy chaining - using only 1 TS5MP646 Switch IC - you could create essentially a 1:1 switch with 3 channels. Where the IC is disconnected from all headers or connected to all of the headers. If this is what you are trying to achieve there are risks associated with it.

    1. If all of the headers are connected - the current going through the first switch will be a combination of all the header current going through the switch if this exceeds +/- 35mA then the switch could be damaged during operation. Also the higher current could degrade the voltage over the switch more than having only 1 header attached which could cause data corruption if the voltage drop is too large

    2. The 2nd and 3rd header are going to go through multiple switching pathways - this is going to attenuate their signal more than the signal at the first jumper.

    If I am misunderstanding how you plan to use daisy chaining please let me know!

    Unused Pins Floating

    In Higher speed applications - such as CSI2 it is recommended to terminate unused I/O pins with a 50 Ohm resistor to Ground.

    1:3 MIPI Switch

    We do not have a 1:3 MIPI switch - our MIPI switches fall under the 1:2 (SPDT)  switches. A 3:1 configuration can be made by creating a 4:1 switch out of 2:1 switches. Two of the 2:1 switch will form a 4:1 mux front end. The output of the first stage is output into the second stage which is another 2:1 switch. These devices will operate as a 4:1 switch with 2 control bits.  The unused port can be terminated to ground using a 50 Ohm resistor. This is typically preferred compared to the daisy chain as all 3 headers will get roughly the same signal from the IC when the header is chosen.

    Please if you can answer my couple questions I had for you so I can make sure that I recommend the best solution for the application you are facing. If you have any additional questions or would like clarification on anything that I have said above please let me know !

    Best,

    Parker Dodson

  • 0 in reply to Parker Dodson
    TI__Mastermind 33805 points

    Hi,

    1. What we need is for the output of the IC to be connected to 1 header per time, there will be 3 headers, we don't need all headers at once 
    2. CSI-2 lane, so 4 data pairs and the clock.
    3. Since what we need is the 3:1 SP3T switch, is there any data integrity risk by using two of the 2:1 switch will form a 4:1 mux front end?

    Regards,

    Charles O

  • 0 in reply to Charles Oladimeji
    TI__Guru 52352 points

    Hi Charles,

    Alright I understand completely.  There are a few more considerations when using this configuration:

    1. In HS mode for CSI-2 the RON  is typically 6 ohms with a max (at max temperature) at 9 Ohms. With Two switches in-between the on resistance of the switch structure would typically be around 12 Ohms - which is going to be a larger attenuation from the switch structure.

    i.e.) Load is 100 Ohms, On resistance is 12 Ohms, Percentage of Source Voltage on Load: 100/112 ~ 89.29%. Lose ~11% of signal over the switch structure typically.  Compared to the using just 1 switch (6 ohms) which would be: 100/106 ~ 94.34% which would Lose ~5.66% of the signal over the switch. Unless you are running the switch near max conditions at all times - you can more reasonably expect to land around the typical value.

    2. When a switch pathway is chosen the on resistances and On capacitances can be combined to create a larger RC circuit. This additional capacitance would lower bandwidth a bit (but at the frequency you are looking at - it shouldn't be a major problem). However it will increase the prop delay through the switch since the on capacitance will also effectively double of the activated switch pathway.

    3. Layout considerations will be much more important  as connection between the three IC's must be symmetrical to help prevent signal integrity issues due layout between the IC's.

    4. On Resistance Mismatch - there is some mismatch between channels - this can possibly be compounded by using two switch pathways in series - but it is typically 0.1 Ohms and shouldn't have that much of a negative effect on the output channel.

    If the application can handle the attenuation presented than there shouldn't be an issue. However using buffers at the end to try to regain some of the lost voltage is always a possibility in case the attenuation is too much of a risk. 

     

    If you have any other further questions or would like any clarification please let me know and I will see what I can do!

    Best,

    Parker Dodson