e2e,
I'm currently using the TS5A33157-Q1 to pass an I2C signal. Due to my system requirements, I would like to operate this mux at 1.8V supply voltage but concerned that the on-state resistance and capacitance at that supply voltage will impact the rising edge of my I2C signal.
I didn't see an IBIS model available for this mux to use in my simulation so I would like your recommendation on how to model this device in my simulation.
Thank you,
Adam
Thank you,
Adam
Hi Adam,
The TS5A33157-Q1 will impact the rise time of the I2C signal - However it shouldn't throw the application out of I2C specifications.
In our electrical specifications table we specify a max Ron_peak value of 150 Ohms across temp range:
A few things to note:
Ron was measured at a VDD of 1.65 Ohms - this means at 1.8V the channel resistance may be slightly smaller - but not larger than 150 Ohms. This is also the peak value - and it will not hold across the voltage range - typically when not in its peak range - it will max out around 50 ohms. However the peak value when using this device at 1.8V (full temp range) is not going to be higher than 150 Ohms.
As for capacitance we give a typical value of 17pF of added bus capacitance when the switch is closed.
I2C spec gives the follow specs for timing and max bus capacitance:
We also have the following thresholds:
VIH(min) = 0.7 * VDD = 1.26V
VIL(max) = 0.3 * VDD = 540mV
The mux can be seen as a simple RC circuit - and the I2C buffer input is a high impedance load. So for Rise/Fall time we can look at the RC created by the on resistance of the Multiplexer, its parasitic capacitance, and other devices on the line.
To simulate worst case scenario I set up the following circuit:
R1 is the worst case On Resistance for the device.
C1 is the maximum allowable bus capacitance for I2C
R2 is a simulated "High Impedance Load" to simulate the receiving I2C buffer.
For the Standard Mode Simulation I used:
frequency: 100KHz
rise time: 1us (worst case for I2C spec)
fall time: 300ns (worst case for I2C spec)
In Worst Case Conditions the rise time will not be in violation of spec and will operate correctly for standard mode:
High Time: 4.36us > 4 us required for standard mode
Low Time: 5.04us > 4.7us required for standard mode
For Fast Mode the following test was used:
Frequency: 400KHz
Rise Time = Fall Time = 300ns
As with the standard mode simulation:
High Time = ~766ns > 600ns minimum that is required by fast mode
Low Time = 1.47us > 1.3us minimum that is required by fast mode
For Fast Mode + the following parameters were used
frequency = 1MHz
rise/fall time = 120ns (worst case)
Bus Capacitance = 550pF
As in the other two scenarios we are still within I2C spec even using Fast Mode +
High Time: 301ns > 260ns minimum required by spec
Low Time: 542ns > 500ns minimum required by spec.
A Few notes for clarification:
1. This is absolute worst case simulations - assuming that bus capacitance has been maxed out which depends on the setup - but if it is just the transmitter, receiver, pull-up resistors, and the mux on the line this value will most likely < 400pF for standard/fast mode and <550pF for Fast+ mode.
2. Ron will not be 150 ohms for the entire signal range - it will only peak at one point during the signal rise. The simulation assumed its always at 150 ohms - and not less so the simulation performed is conservative and should perform better that what is shown.
3. If more margin is desired than what is being shown bumping up the power rail for the IC to 3.3V will give a lot more margin - however it doesn't see necessary.
If you have any other questions please let me know!
Best,
Parker Dodson
