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TS3V713EL: Some questions about TS7V713EL

Oliver Ou
Intellectual 2845 points
Part Number: TS3V713EL

Hi Expert, 

Customer has some questions about TS3V713EL:

1. About IC's PIN16 VDD_5, dose it need a leakage current protection design?

2. About IC's Pin8,  dose it need PU design or float it directly?

3. what's the driving capability?

 Could you help to check and give some comments?

Thanks,

Oliver Ou

  • 0
    TI__Intellectual 2694 points

    Hi Oliver,

    Please see the response below for the TS3V713EL device.

    1. About IC's PIN16 VDD_5, dose it need a leakage current protection design?

    A: The VDD_5 (Pin 16) is the supply pin for the buffer/translator on the Hx/Vx channels. The device does not require any current limiting resistor unless you see a system scenario where the device will end up pulling in higher than the absolute maximum current (100mA). The customer can always add a 0ohm resistor in case there is any concern that will allow them to make changes if needed in the future.

    2. About IC's Pin8,  dose it need PU design or float it directly?

    A: The Pin 8 is N.C. (no connect) pin and does not have any bond wire. It can be left floating or connected to Pull-up if board already has pull-ups. There will be no impact on the device operation.

    3. What's the driving capability?

    A: The R, G, B and SCL, SDA channels are pass-fet type architecture so the driver capability is dependent on the external driver on the input side (0) or output side (1, 2). Make sure the pull-ups exists on the SCL/SDA lines as these are open drain pins due to I2C architecture. The H, V pins have a buffer and a IOH/IOL specification of -8/+8mA as specified in the recommended operating conditions table.

    Hope this helps.

    Thank you,

    Regards,
    Sandesh

  • 0 in reply to Sandesh Rawool
    TI__Intellectual 2845 points

    Hi Sandesh,

    Thanks a lot for your detail explanation.

    Board supply 5V to VDD_5 pin but  other VDD pins supply voltage is 0V. is there any leakage current from VDD_5 pin to other pins at this condition? 

    Thanks.

    Oliver Ou

  • 0 in reply to Oliver Ou
    TI__Intellectual 2694 points

    Hi Oliver,

    The VDD and VDD_5 can be powered independently as seen from the absolute maximum table.

    When both the supplies are powered off (0V), any voltage on I/O pins will create a small IOFF leakage of +/-1uA.

    When one of the supplies is powered, in this case VDD_5, even though only the H, V pins are powered using VDD_5 supply for buffer/translation, there is always an internal reference that comes from VDD and will create a leakage path depending on the voltages on other pins. This will not be damaging the device but there will be leakage and will be close to the IOFF.

    Thank you,

    Regards,
    Sandesh