HI,
Parts like TMUX1574, tend to only only list the typical propagation delay in the data sheet.. How should i determine the max propagation delay? Is it listed elsewhere or should I derive it from another specification? Please explain best approach.
Thank you,
HSG
Hi HSG,
We don't typically don't spec min/max propagation delay as it depends on application scenario.
However, you can approximate it.
First - the active mux pathway can be modeled as a simple RC with the resistance being the on resistance of the multiplexer and the capacitance being the on Capacitance of the multiplexer. The load of the mux can typically be seen as a simple RC block in parallel. This is shown below with the Load shown in the dashed box.
Since the parasitic capacitance on the load is in parallel with the on capacitance these can be added together. This combined capacitor can now be treated as the load - shown below.
If we treat the capacitor as the load - we can find the Thevenin Resistance of the model by shorting the supply and opening the load.
The equivalent resistance as seen by the load is the Thevenin Resistance - which in this case is R_th = (R_On * R_Load)/(R_On + R_Load)
This gives us an RC of = R_th * (C_on + C_Load). Approximately 1 time constant is equal to the propagation delay.
For worst case approximation use the max R_On and max C_On. This approach will be liberal in its results as max R_On and C_On don't occur in most situations. To tailor this the following tables can be used: (A 5.5V supply is used but the TMUX1574 has Ron charts for other supplies as well.)
Also Capacitance can be found and it will vary the most with frequency - as shown below:
If the system setup is a bit more complex than that SPICE based simulators can help model the propagation delay by using passive components to model the signal chain and then measuring the prop delay between the input and output of mux.
Package parasitics and layout also contribute to propagation delay. Package parasitics can be found in the IBIS file - they will give R/L/C values of the pins of the package on the IC. An equivalent passive element model of an active mux pathway with package is shown below:
This model will help give a closer estimation of prop delay that you could see in the system - Plug this into a spice simulation with the correct input and loading conditions to get the closest approximation.
If you have any other questions please let me know and I will see what I can do!
Best,
Parker Dodson
