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UniFlash 6.3.0.3193 : Verifying CPU2 First Stops CPU1 From Verifying

Other Parts Discussed in Thread: UNIFLASH

Hello,

I have a dual CPU project for LAUNCHXL-F8379D that runs standalone. I have already flashed the CPUs.

After a fresh launch of UniFlash, verification succeeds on both CPUs but only if I verify in the order CPU1 then CPU2.

If verification is done in the order CPU2 then CPU1, the latter is not executed. The Verify Program window very, very briefly flashes up but nothing meaningful happens there and there's no console entry. The steps to reproduce are:

Launch UniFlash

Verify CPU1 : OK

Verify CPU2 : OK

Verify CPU1 : OK

Verify CPU2 : OK

Restart UniFlash

Verify CPU2 : OK

Verify CPU1 : No meaningful verification, no console entry.

Verify CPU2 : OK

Verify CPU1 : No meaningful verification, no console entry.

Verify CPU2 : OK

Log Before Restart:

[29/06/2021 08:37:47] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[29/06/2021 08:37:48] [INFO] C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
[29/06/2021 08:37:51] [SUCCESS] C28xx_CPU1: Program verification successful for W:/Build/OBC_CPU1/CPU1_FLASH/OBC_CPU1.hex
[29/06/2021 08:37:54] [INFO] C28xx_CPU2: GEL Output: Memory Map Initialization Complete
[29/06/2021 08:37:54] [INFO] C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
[29/06/2021 08:37:55] [SUCCESS] C28xx_CPU2: Program verification successful for W:/Build/OBC_CPU2/CPU2_FLASH/OBC_CPU2.hex
[29/06/2021 08:38:03] [SUCCESS] C28xx_CPU1: Program verification successful for W:/Build/OBC_CPU1/CPU1_FLASH/OBC_CPU1.hex
[29/06/2021 08:38:08] [SUCCESS] C28xx_CPU2: Program verification successful for W:/Build/OBC_CPU2/CPU2_FLASH/OBC_CPU2.hex

Log After Restart:

[29/06/2021 08:49:03] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[29/06/2021 08:49:04] [INFO] C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
[29/06/2021 08:49:04] [INFO] C28xx_CPU2: GEL Output: Memory Map Initialization Complete
[29/06/2021 08:49:04] [INFO] C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
[29/06/2021 08:49:05] [SUCCESS] C28xx_CPU2: Program verification successful for W:/Build/OBC_CPU2/CPU2_FLASH/OBC_CPU2.hex
[29/06/2021 08:49:16] [SUCCESS] C28xx_CPU2: Program verification successful for W:/Build/OBC_CPU2/CPU2_FLASH/OBC_CPU2.hex