CCS11 : Error connecting to the target: (Error -1265 @ 0x0)

Hello,

When you open up 'Device Manager' on your computer do you see the debug probe listed? What is the status of the LEDs on the XDS560v2?

The drivers may not have been installed when you downloaded CCS. Can you please try running the following utility: SD560v2Config.exe, which is installed with CCS and can be found at the directory below:

<CCS_INSTALL_DIR>/ccs/ccs_base/common/uscif

Another alternative could be re-installing CCS and ensuring that the support for Spectrum Digital debug probes is checked.

Helpful Link for XDS560v2: https://dev.ti.com/tirex/explore/node?node=AMCtoFmXB.aqHFNswmb6Dg__FUz-xrs__LATEST 

Best Regards,

Marlyn 

Invalid device ID suggests the "Device ID is not recognized or is not supported by driver" is a likely a hardware failure on the board, or interference on the JTAG signals, rather than a problem with the debug probe drivers on the host PC.

Hello.

Thanks to reply.

The debug prove listed named 'Spectrum Digital XDS560v2 USB' in Device Mansger.

and Status of the LEDs is State-2 and State-3 lights up.

I Try running 'SD560v2Config.exe'. and the result is below.

@BEGIN-1
MSG: NUMBER OF EMULATORS CONNECTED : 1

PRODUCT SERIAL NUMBER ADDRESS
---------------------------------------------------------------------------------------------------------------------
XDS560V2 STM S560-000E9903E5DF 25545500
@END-1

Test Connection(in *ccxml) result is below.

[Start: Spectrum Digital XDS560V2 STM USB Emulator_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

C:\Users\A507901\AppData\Local\TEXASI~1\
CCS\ccs1100\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'sd560v2u.out'.
Loaded FPGA Image: C:\ti\ccs1100\ccs\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Oct 8 2021'.
The library build time was '17:43:59'.
The library package version is '9.5.0.00143'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccs1100\ccs\ccs_base\common\uscif\dtc_top.jbc

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 none - 01 00 500.0kHz - similar isit internal clock
2 none - 01 09 570.3kHz - similar isit internal clock
3 64 - 01 00 500.0kHz O good value measure path length
4 16 - 01 00 500.0kHz O good value auto step initial
5 16 - 01 0D 601.6kHz O good value auto step delta
6 16 - 01 1C 718.8kHz O good value auto step delta
7 16 - 01 2E 859.4kHz O good value auto step delta
8 16 + 00 02 1.031MHz O good value auto step delta
9 16 + 00 0F 1.234MHz O good value auto step delta
10 16 + 00 1F 1.484MHz O good value auto step delta
11 16 + 00 32 1.781MHz O good value auto step delta
12 16 + 01 04 2.125MHz O good value auto step delta
13 16 + 01 11 2.531MHz O good value auto step delta
14 16 + 01 21 3.031MHz O good value auto step delta
15 16 + 01 34 3.625MHz O good value auto step delta
16 16 + 02 05 4.313MHz O good value auto step delta
17 16 + 02 13 5.188MHz O good value auto step delta
18 16 + 02 23 6.188MHz O good value auto step delta
19 16 + 02 37 7.438MHz O good value auto step delta
20 16 + 03 07 8.875MHz O good value auto step delta
21 16 + 03 15 10.63MHz O good value auto step delta
22 16 + 03 1E 11.75MHz {O} good value auto step delta
23 64 + 02 3E 7.875MHz O good value auto power initial
24 64 + 03 0E 9.750MHz O good value auto power delta
25 64 + 03 16 10.75MHz O good value auto power delta
26 64 + 03 1A 11.25MHz O good value auto power delta
27 64 + 03 1C 11.50MHz O good value auto power delta
28 64 + 03 1D 11.63MHz O good value auto power delta
29 64 + 03 1D 11.63MHz O good value auto power delta
30 64 + 03 13 10.38MHz {O} good value auto margin initial

The first internal/external clock test resuts are:
The expect frequency was 500000Hz.
The actual frequency was 499110Hz.
The delta frequency was 890Hz.

The second internal/external clock test resuts are:
The expect frequency was 570312Hz.
The actual frequency was 569214Hz.
The delta frequency was 1098Hz.

In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 12 bits.
The JTAG DR length was 2 bits.

The IR/DR scan-path tests used 30 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 11.75MHz as the highest frequency.
The IR/DR scan-path tests used 10.38MHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

The frequency of the JTAG TCLKR input is measured as 10.37MHz.

The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
The target system likely uses the TCLKO output from the emulator PLL.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 12 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 2 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Spectrum Digital XDS560V2 STM USB Emulator_0]

And I re-installed CCS.

I can't find why it dosen't work.

Thanks.

hello.

I tested it in 4 places with the same board and debugger, and the same error occurred in 3 places.

Seeing that it worked properly in last one place, it seems that it is not a problem with the board and the debugger.

I used the same Setting of CCS and Code(C2000ware examples).

Thanks.

Hong joo Kam said:

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 12 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 2 bits.

The JTAG test connection reported a pass. However, the reported JTAG IR instruction path-length is 12 bits. Whereas from the TMS320F28388D BSDL in sprm745.zip expect the JTAG IR instruction path-length to be 6 bits.

I don't have a TMS320F28388D to check what the test connection reports for the JTAG IR instruction path-length and JTAG DR bypass pass-length for a working device, but can you run the test connection in all 4 places and check if the path-lengths are reported the same values for the working and non-working place?

While it for a different device, found C55xx: Error connecting to the target: (Error -1063 @ 0x0) Device ID is not recognized or is not supported by driver which has some explanation on how the debugger might read the wrong device ID if the JTAG path-lengths are wrong.

Perhaps trying to slow down the JTAG TCLK Frequency would help. E.g. in the Target Configuration try setting "JTAG TCLK Frequency (MHz)" to "Automatic with user specified limit" and say a maximum frequency of 1 MHz :

If the JTAG IR instruction path-length is reading back as double the expected value maybe there is an issue at the higher speeds.