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TDA3XEVM: convert gcc ARM assambly code to ti ARM compiler Assembly code

Part Number: TDA3XEVM

The following assambly source code is original for gcc arm complier, I did some changes for TI ARM compiler, but there are still some build issues.

[E0004]
Illegal constant, does not conform to modify_constant() format
and r9,r8,#-38

[E0004]
Illegal constant, does not conform to modify_constant() format
and r12,r4,#0x7fffffff

   .thumb
   .text
   .align 2
fe25519_add:
   .global fe25519_add
   ldr r0,[r8,#28]
   ldr r4,[r9,#28]
   adds r0,r0,r4
   mov r11,#0
   adc r11,r11,r11
   lsl r11,r11,#1
   add r11,r11,r0, lsr #31
   movs r7,#19
   mul r11,r11,r7
   bic r7,r0,#0x80000000
   ldm r8!,{r0-r3}
   ldm r9!,{r4-r6,r10}
   mov r12,#1
   umaal r0,r11,r12,r4
   umaal r1,r11,r12,r5
   umaal r2,r11,r12,r6
   umaal r3,r11,r12,r10
   ldm r9,{r4-r6}
   ldm r8,{r8-r10}
   umaal r4,r11,r12,r8
   umaal r5,r11,r12,r9
   umaal r6,r11,r12,r10
   add r7,r7,r11
   bx lr
fe25519_sub:
   .global fe25519_sub
   ldm r8,{r0-r7}
   ldm r9!,{r8,r10-r12}
   subs r0,r8
   sbcs r1,r10
   sbcs r2,r11
   sbcs r3,r12
   ldm r9,{r8-r11}
   sbcs r4,r8
   sbcs r5,r9
   sbcs r6,r10
   sbcs r7,r11
   sbc r8,r8
   and r9,r8,#-38
   adds r0,r9
   adcs r1,r8
   adcs r2,r8
   adcs r3,r8
   adcs r4,r8
   adcs r5,r8
   adcs r6,r8
   adcs r7,r8
   adcs r8,#0
   and r9,r8,#-38
   adds r0,r9
   bx lr
fe25519_mul:
   .global fe25519_mul
   push {r2,lr}
   sub sp,#28
   ldm r2,{r2,r3,r4,r5}
   ldm r1!,{r0,r10,lr}
   umull r6,r11,r2,r0
   umull r7,r12,r3,r0
   umaal r7,r11,r2,r10
   push {r6,r7}
   umull r8,r6,r4,r0
   umaal r8,r11,r3,r10
   umull r9,r7,r5,r0
   umaal r9,r11,r4,r10
   umaal r11,r7,r5,r10
   umaal r8,r12,r2,lr
   umaal r9,r12,r3,lr
   umaal r11,r12,r4,lr
   umaal r12,r7,r5,lr
   ldm r1!,{r0,r10,lr}
   umaal r9,r6,r2,r0
   umaal r11,r6,r3,r0
   umaal r12,r6,r4,r0
   umaal r6,r7,r5,r0
   strd r8,r9,[sp,#8]
   mov r9,#0
   umaal r11,r9,r2,r10
   umaal r12,r9,r3,r10
   umaal r6,r9,r4,r10
   umaal r7,r9,r5,r10
   mov r10,#0
   umaal r12,r10,r2,lr
   umaal r6,r10,r3,lr
   umaal r7,r10,r4,lr
   umaal r9,r10,r5,lr
   ldr r8,[r1],#4
   mov lr,#0
   umaal lr,r6,r2,r8
   umaal r7,r6,r3,r8
   umaal r9,r6,r4,r8
   umaal r10,r6,r5,r8
   ldr r8,[r1],#-28
   mov r0,#0
   umaal r7,r0,r2,r8
   umaal r9,r0,r3,r8
   umaal r10,r0,r4,r8
   umaal r6,r0,r5,r8
   push {r0}
   ldr r2,[sp,#40]
   adds r2,r2,#16
   ldm r2,{r2,r3,r4,r5}
   ldr r8,[r1],#4
   mov r0,#0
   umaal r11,r0,r2,r8
   str r11,[sp,#16+4]
   umaal r12,r0,r3,r8
   umaal lr,r0,r4,r8
   umaal r0,r7,r5,r8
   ldr r8,[r1],#4
   mov r11,#0
   umaal r12,r11,r2,r8
   str r12,[sp,#20+4]
   umaal lr,r11,r3,r8
   umaal r0,r11,r4,r8
   umaal r11,r7,r5,r8
   ldr r8,[r1],#4
   mov r12,#0
   umaal lr,r12,r2,r8
   str lr,[sp,#24+4]
   umaal r0,r12,r3,r8
   umaal r11,r12,r4,r8
   umaal r10,r12,r5,r8
   ldr r8,[r1],#4
   mov lr,#0
   umaal r0,lr,r2,r8
   str r0,[sp,#28+4]
   umaal r11,lr,r3,r8
   umaal r10,lr,r4,r8
   umaal r6,lr,r5,r8
   ldm r1!,{r0,r8}
   umaal r11,r9,r2,r0
   str r11,[sp,#32+4]
   umaal r9,r10,r3,r0
   umaal r10,r6,r4,r0
   pop {r11}
   umaal r11,r6,r5,r0
   umaal r9,r7,r2,r8
   umaal r10,r7,r3,r8
   umaal r11,r7,r4,r8
   umaal r6,r7,r5,r8
   ldm r1!,{r0,r8}
   umaal r10,r12,r2,r0
   umaal r11,r12,r3,r0
   umaal r6,r12,r4,r0
   umaal r7,r12,r5,r0
   umaal r11,lr,r2,r8
   umaal r6,lr,r3,r8
   umaal lr,r7,r4,r8
   umaal r7,r12,r5,r8
   ldrd r4,r5,[sp,#28]
   movs r3,#38
   mov r8,#0
   umaal r4,r8,r3,r12
   lsl r8,r8,#1
   orr r8,r8,r4, lsr #31
   and r12,r4,#0x7fffffff
   movs r4,#19
   mul r8,r8,r4
   pop {r0-r2}
   umaal r0,r8,r3,r5
   umaal r1,r8,r3,r9
   umaal r2,r8,r3,r10
   mov r9,#38
   pop {r3,r4}
   umaal r3,r8,r9,r11
   umaal r4,r8,r9,r6
   pop {r5,r6}
   umaal r5,r8,r9,lr
   umaal r6,r8,r9,r7
   add r7,r8,r12
   add sp,#12
   pop {pc}
fe25519_sqr:
   .global fe25519_sqr
   push {lr}
   sub sp,#20
   umull r9,r10,r0,r0
   umull r11,r12,r0,r1
   adds r11,r11,r11
   mov lr,#0
   umaal r10,r11,lr,lr
   push {r9,r10}
   mov r8,#0
   umaal r8,r12,r0,r2
   adcs r8,r8,r8
   umaal r8,r11,r1,r1
   umull r9,r10,r0,r3
   umaal r9,r12,r1,r2
   adcs r9,r9,r9
   umaal r9,r11,lr,lr
   strd r8,r9,[sp,#8]
   mov r9,#0
   umaal r9,r10,r0,r4
   umaal r9,r12,r1,r3
   adcs r9,r9,r9
   umaal r9,r11,r2,r2
   str r9,[sp,#16]
   umull r9,r8,r0,r5
   umaal r9,r10,r1,r4
   umaal r9,r12,r2,r3
   adcs r9,r9,r9
   umaal r9,r11,lr,lr
   str r9,[sp,#20]
   mov r9,#0
   umaal r9,r8,r1,r5
   umaal r9,r12,r2,r4
   umaal r9,r10,r0,r6
   adcs r9,r9,r9
   umaal r9,r11,r3,r3
   str r9,[sp,#24]
   umull r0,r9,r0,r7
   umaal r0,r10,r1,r6
   umaal r0,r12,r2,r5
   umaal r0,r8,r3,r4
   adcs r0,r0,r0
   umaal r0,r11,lr,lr
   umaal r9,r8,r1,r7
   umaal r9,r10,r2,r6
   umaal r12,r9,r3,r5
   adcs r12,r12,r12
   umaal r11,r12,r4,r4
   umaal r9,r8,r2,r7
   umaal r10,r9,r3,r6
   movs r2,#0
   umaal r10,r2,r4,r5
   adcs r10,r10,r10
   umaal r12,r10,lr,lr
   umaal r2,r8,r3,r7
   umaal r9,r2,r4,r6
   adcs r9,r9,r9
   umaal r10,r9,r5,r5
   movs r3,#0
   umaal r3,r8,r4,r7
   umaal r3,r2,r5,r6
   adcs r3,r3,r3
   umaal r9,r3,lr,lr
   umaal r8,r2,r5,r7
   adcs r8,r8,r8
   umaal r3,r8,r6,r6
   umull r4,r5,lr,lr
   umaal r4,r2,r6,r7
   adcs r4,r4,r4
   umaal r4,r8,lr,lr
   adcs r2,r2,r2
   umaal r8,r2,r7,r7
   adcs r2,r2,lr
   mov r6,#38
   umaal r0,lr,r6,r2
   lsl lr,lr,#1
   orr lr,lr,r0, lsr #31
   and r7,r0,#0x7fffffff
   movs r5,#19
   mul lr,lr,r5
   pop {r0,r1}
   umaal r0,lr,r6,r11
   umaal r1,lr,r6,r12
   mov r11,r3
   mov r12,r4
   pop {r2,r3,r4,r5}
   umaal r2,lr,r6,r10
   umaal r3,lr,r6,r9
   umaal r4,lr,r6,r11
   umaal r5,lr,r6,r12
   pop {r6}
   mov r12,#38
   umaal r6,lr,r12,r8
   add r7,r7,lr
   pop {pc}
fe25519_sqr_many:
   .global fe25519_sqr_many
   push {r8,lr}
$0:
   bl fe25519_sqr
   ldr r8,[sp,#0]
   subs r8,r8,#1
   str r8,[sp,#0]
   bne $0
   .newblock ; Undefine $0 so it can be used
   add sp,sp,#4
   add r8,sp,#4
   stm r8,{r0-r7}
   pop {pc}
loadm:
   ldr r0,[r1,#0]
   ldr r2,[r1,#8]
   ldr r3,[r1,#12]
   ldr r4,[r1,#16]
   ldr r5,[r1,#20]
   ldr r6,[r1,#24]
   ldr r7,[r1,#28]
   ldr r1,[r1,#4]
   bx lr
curve25519_scalarmult:
   .global curve25519_scalarmult
   push {r0,r4-r11,lr}
   mov r10,r2
   bl loadm
   and r0,r0,#0xfffffff8
   orr r7,r7,#0x40000000
   push {r0-r7}
   movs r8,#0
   push {r2,r8}
   mov r1,r10
   bl loadm
   and r7,r7,#0x7fffffff
   push {r0-r7}
   movs r9,#1
   umull r10,r11,r8,r8
   mov r12,#0
   push {r8,r10,r11,r12}
   push {r9,r10,r11,r12}
   push {r0-r7}
   umull r6,r7,r8,r8
   push {r6,r7,r8,r10,r11,r12}
   push {r6,r7,r8,r10,r11,r12}
   push {r9,r10,r11,r12}
   movs r0,#254
   movs r3,#0
$0:
   lsrs r1,r0,#5
   adds r2,sp,#168
   ldr r1,[r2,r1,lsl #2]
   and r4,r0,#0x1f
   lsrs r1,r1,r4
   and r1,r1,#1
   strd r0,r1,[sp,#160]
   eors r1,r1,r3
   rsbs lr,r1,#0
   mov r0,sp
   add r1,sp,#64
   mov r11,#4
$1:
   ldm r0,{r2-r5}
   ldm r1,{r6-r9}
   eors r2,r2,r6
   and r10,r2,lr
   eors r6,r6,r10
   eors r2,r2,r6
   eors r3,r3,r7
   and r10,r3,lr
   eors r7,r7,r10
   eors r3,r3,r7
   eors r4,r4,r8
   and r10,r4,lr
   eors r8,r8,r10
   eors r4,r4,r8
   eors r5,r5,r9
   and r10,r5,lr
   eors r9,r9,r10
   eors r5,r5,r9
   stm r0!,{r2-r5}
   stm r1!,{r6-r9}
   subs r11,#1
   bne $1
   mov r8,sp
   add r9,sp,#32
   bl fe25519_add
   push {r0-r7}
   bl fe25519_sqr
   push {r0-r7}
   add r8,sp,#64
   add r9,sp,#96
   bl fe25519_sub
   push {r0-r7}
   bl fe25519_sqr
   push {r0-r7}
   mov r1,sp
   add r2,sp,#64
   bl fe25519_mul
   add r8,sp,#128
   stm r8,{r0-r7}
   add r8,sp,#64
   mov r9,sp
   bl fe25519_sub
   add r8,sp,#64
   stm r8,{r0-r7}
   mov lr,#56130
   add lr,lr,#65536
   ldr r12,[sp,#28]
   mov r11,#0
   umaal r12,r11,lr,r7
   lsl r11,r11,#1
   add r11,r11,r12, lsr #31
   movs r7,#19
   mul r11,r11,r7
   bic r7,r12,#0x80000000
   ldm sp!,{r8,r9,r10,r12}
   umaal r8,r11,lr,r0
   umaal r9,r11,lr,r1
   umaal r10,r11,lr,r2
   umaal r12,r11,lr,r3
   ldm sp!,{r0,r1,r2}
   umaal r0,r11,lr,r4
   umaal r1,r11,lr,r5
   umaal r2,r11,lr,r6
   add r7,r7,r11
   add sp,sp,#4
   push {r0,r1,r2,r7}
   push {r8,r9,r10,r12}
   mov r1,sp
   add r2,sp,#64
   bl fe25519_mul
   add r8,sp,#160
   stm r8,{r0-r7}
   add r8,sp,#192
   add r9,sp,#224
   bl fe25519_add
   stm sp,{r0-r7}
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add r8,sp,#32
   stm r8,{r0-r7}
   add r8,sp,#192
   add r9,sp,#224
   bl fe25519_sub
   stm sp,{r0-r7}
   mov r1,sp
   add r2,sp,#96
   bl fe25519_mul
   stm sp,{r0-r7}
   mov r8,sp
   add r9,sp,#32
   bl fe25519_add
   bl fe25519_sqr
   add r8,sp,#192
   stm r8,{r0-r7}
   mov r8,sp
   add r9,sp,#32
   bl fe25519_sub
   bl fe25519_sqr
   stm sp,{r0-r7}
   mov r1,sp
   add r2,sp,#256
   bl fe25519_mul
   add r8,sp,#224
   stm r8,{r0-r7}
   add sp,sp,#128
   ldrd r2,r3,[sp,#160]
   subs r0,r2,#1
   bpl $0
   .newblock ; Undefine $0 and S1 so it can be used
   add r0,sp,#32
   ldm r0,{r0-r7}
   bl fe25519_sqr
   push {r0-r7}
   bl fe25519_sqr
   bl fe25519_sqr
   push {r0-r7}
   add r1,sp,#96
   mov r2,sp
   bl fe25519_mul
   stm sp,{r0-r7}
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add r8,sp,#32
   stm r8,{r0-r7}
   bl fe25519_sqr
   push {r0-r7}
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add r8,sp,#32
   stm r8,{r0-r7}
   mov r8,#5
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add r8,sp,#32
   stm r8,{r0-r7}
   movs r8,#10
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   stm sp,{r0-r7}
   movs r8,#20
   sub sp,sp,#32
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add sp,sp,#32
   movs r8,#10
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add r8,sp,#32
   stm r8,{r0-r7}
   movs r8,#50
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   stm sp,{r0-r7}
   movs r8,#100
   sub sp,sp,#32
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   add sp,sp,#32
   movs r8,#50
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#32
   bl fe25519_mul
   movs r8,#5
   bl fe25519_sqr_many
   mov r1,sp
   add r2,sp,#64
   bl fe25519_mul
   stm sp,{r0-r7}
   mov r1,sp
   add r2,sp,#96
   bl fe25519_mul
   lsr r8,r7,#31
   mov r9,#19
   mul r8,r8,r9
   mov r10,#0
   add r8,r8,#19
   adds r8,r0,r8
   adcs r8,r1,r10
   adcs r8,r2,r10
   adcs r8,r3,r10
   adcs r8,r4,r10
   adcs r8,r5,r10
   adcs r8,r6,r10
   adcs r8,r7,r10
   adcs r11,r10,r10
   lsr r8,r8,#31
   orr r8,r8,r11, lsl #1
   mul r8,r8,r9
   ldr r9,[sp,#296]
   adds r0,r0,r8
   str r0,[r9,#0]
   movs r0,#0
   adcs r1,r1,r0
   str r1,[r9,#4]
   mov r1,r9
   adcs r2,r2,r0
   adcs r3,r3,r0
   adcs r4,r4,r0
   adcs r5,r5,r0
   adcs r6,r6,r0
   adcs r7,r7,r0
   and r7,r7,#0x7fffffff
   str r2,[r1,#8]
   str r3,[r1,#12]
   str r4,[r1,#16]
   str r5,[r1,#20]
   str r6,[r1,#24]
   str r7,[r1,#28]
   add sp,sp,#300
   pop {r4-r11,pc}

  • I apologize for the delay.

    The Cortex-M4 CPU only supports encoding certain constants within the instruction.  For the AND instruction, a 12-bit field in the instruction is used for the constant.  To understand how it is used, please see this description from arm.com.  Focus on the part that describes how the constants are encoded in the instruction, and ignore the rest.  When the assembler cannot encode the constant given, it issues the error diagnostic you see.  In your case, you can use the BIC instruction (it stands for bit instruction clear) instead, with a constant that is the inverse of the one used with the AND instruction.  Here are some examples ...

       ; and r9,r8,#-38
       bic r9,r8,#37
    
       ; and r12,r4,#0x7fffffff
       bic r12,r4,#0x80000000
    
       ; and r0,r0,#0xfffffff8
       bic r0,r0,#7

    Thanks and regards,

    -George

  • Hi George, thank you, it can work now