We have hit into a very strange issue with the CCSv4.2.3
Here is the scenario.
What we are doing: verifying data transfer from a signal path FPGA to the DSP DDR memory.
Setup: Stratix IV FPGA EVM connected to 6472 Rev4 EVM over SRIO (single port).
CCSv4 version 4.2.3
We load DSP code using CCSv4 and load FPGA using Altera FPGA tool.
Gel file used: evmc6272.gel provided as part of CCSv4 installation
What we have observed: the memory content (as seen using CCS memory window), after running the test is not consistent. Occasionally (but rare) we see the right data in the memory window.
It is not cache related since cache is not enabled.
However, if we press ALT-S in CCSv4, the right data shows up in memory window.
We then did another experiment. Keeping the HW setup as is, we used a different PC for CCSv4. This PC has CCSv4 version 4.2.1. We don’t have the above problem with this setup. It works consistently in this setup.
The second setup uses same DSP project, same gel file and same FPGA build as the first one.
The behavior is repeatable.
Uisng 4.2.1 isntead of 4.2.3 is not a good option for us.