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Cache line sizes for different shared regions ignored?

Carsten Reuter
Prodigy 210 points

Hi,

I am using XDC 3.22.0.09 and just trying to setup different shared regions with different cachline sizes for IPC.

Code in the *.cfg file is as follows:

var SharedRegion0 = xdc.useModule('ti.sdo.ipc.SharedRegion');
SharedRegion0.setEntryMeta(0,
    { base: sharedMem,
      len:  sharedMemSize,
      ownerProcId: 0,
      isValid: true,
      cacheLineSize: 64,
      name: "SHARED_RAM",
    });

var SharedRegion1 = xdc.useModule('ti.sdo.ipc.SharedRegion');
SharedRegion1.setEntryMeta(1,
    { base: 0xE0000000,
      len:  0x00200000,
      ownerProcId: 0,
      isValid: true,
      cacheLineSize: 128,
      name: "SHARED_DDR2",
    });
/*
 *  @(#) ti.sdo.ipc.examples.multicore.evm647x; 1, 0, 0, 0,87; 5-2-2011 16:22:43; /db/vtree/library/trees/ipc/ipc.git/src/ ipc-g16
 */

In CCSv4.2.3 in the Outline Window two SharedRegion items appear. But in the respective Properties Windows the cache line size is 128 for both entities.

When I add

SharedRegion0.cacheLineSize = 128;
SharedRegion1.cacheLineSize = 64;

to the *.cfg file, the cache line size is 64 for both entities.

It seems that only the last .cachlineSize entry is valid.

Are the other SharedRegion options - that are not displayed -  correct?

 

Best regards, Carsten

  • 0
    TI__Guru* 84110 points

    Carsten,

    Cache line size is a fixed property of the caching memory and not a property you can change in the cached memory. What you are doing does not make any sense to me.

    Should I request this thread to be moved to the BIOS forum for XDC help?

    Is this a feature you have seen described somewhere, or did you just want to change a property that you saw in this text file?

    Are you using a simulator and want to change its behavior to be different than how the silicon will behave?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 210 points

    RandyP,

    I know that the cachline size is a fixed feature on the chip. That's why I want it correctly set in the SharedRegion definition.

    SharedRegion is a feature from the IPC module, just have a look in the User Guide SPRUGO6C chapter 3.8.

    I took the source for SharedRegion from the MessageQ example that comes with IPC 1.22, and want to add a SharedRegion in DDR2.

    Regards, Carsten

     

     

  • 0 in reply to Carsten Reuter
    TI__Guru* 84110 points

    Carsten,

    This is something that will be better addressed in the Code Composer forum, since I assume you are using the simulator. If not, I apologize and we will try to get this to the best place.

    It is my expectation that the correct line sizes are already set in the configurations for L1 and L2 memories. I do not believe the Shared Memory includes cache, although it may be cached in L1 and L2 caches. DDR2 definitely does not contain cache, but it can be cached in L1 and L2 caches.

    I do not believe you should be changing these settings. What have you seen in your simulations that leads you to believe the cache settings are incorrect?

    Regards,
    RandyP