error in memory map of omap3530 using RTSC plateform

Hello Everyone,

I am using beagleboard omap3530 with JTAG XDS100v2 on CCSv5.0.2.00006 version.

So, everything running fine, but when i am debugging the even simple hello world program it is showing me error, which i can see in the console window.

Error is something about memory map conflicts or settings.

Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable

Cortex_A8_0: GEL Output: Putting DPLL into bypass before proceeding

Cortex_A8_0: GEL Output: Putting CORE DPLL into bypass before proceeding

Cortex_A8_0: GEL Output: Locking CORE DPLL

Cortex_A8_0: GEL Output: PRCM clock configuration IIA setup has been completed

Cortex_A8_0: GEL Output: SystemClock = 19.2 MHz

Cortex_A8_0: GEL Output: DPLL_MULT_VALUE = 242

Cortex_A8_0: GEL Output: DPLL_DIV_VALUE = 13

Cortex_A8_0: GEL Output: CORE_DPLL_CLK = 663.771 MHz

Cortex_A8_0: GEL Output: CORE_CLK = 331.8855 MHz

Cortex_A8_0: GEL Output: L3_CLK = 165.9427 MHz

Cortex_A8_0: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks

Cortex_A8_0: GEL Output: common_sdram_init() completed

Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed

Cortex_A8_0: GEL Output: 19.2MHz clock configuration IIa

Cortex_A8_0: GEL Output: CORTEXA8_CORE_VERSION = 0x411FC082

Cortex_A8_0: GEL Output: Target contains version r1p2 of the CortexA8...

Cortex_A8_0: GEL Output: Read the ETM_POWER_DOWN_STATUS register...

Cortex_A8_0: GEL Output: ETM_POWER_DOWN_STATUS = 0x00000001

Cortex_A8_0: GEL Output: ETM Access is enabled!

Cortex_A8_0: GEL Output: ETM_ID = 0x410CF232

Cortex_A8_0: GEL Output: ETM Version is: 3.3v2

Cortex_A8_0: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.