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TMS320C6727 Memory Configuration Issues

Derek Rasugu
Prodigy 130 points

Other Parts Discussed in Thread: TMS320C6727, TMS320C6727B

  • 0
    TI__Guru**** 171439 points

    Hi,

    Your message is empty. What is exactly your question?

    Regards,

    Rafael

  • 0 in reply to desouza
    Prodigy 130 points

    Sorry about that. Not sure how that happened. I'm using TMS320C6727 and having problems when using on chip RAM. In particular the "0x10001 XXXX" address range gives me the following errors.

    hex6x romsdirectivetxt.txt

    Translating Debug\DSP1.out to Motorola-S format...

       "Debug\DSP1.out"   ==> .vector

       "Debug\DSP1.out"   ==> .switch

       "Debug\DSP1.out"   ==> .text

       "Debug\DSP1.out"   ==> .const

    >> WARNING: section '.const' at 010010000h falls in unconfigured memory

                (skipped)

       "Debug\DSP1.out"   ==> .cinit

    >> WARNING: section '.cinit' at 010010498h falls in unconfigured memory

                (skipped)

       "Debug\DSP1.out"   ==> .pinit

    >> WARNING: section '.pinit' at 010013420h falls in unconfigured memory

                (skipped)

     

    Clearly the "unconfigured" addresses are well within the address range for this chip. Also I'm using addresses 0x1003F000 and above for my host port and that works fine. My cmd file is as follows.

     

    /****************************************************************************/

    /*  lnk.cmd   v1.10                                                         */

    /*  Copyright (c) 1996-1997  Texas Instruments Incorporated                 */

    /****************************************************************************/

     

     

    -e c_int00

    -c

    -x

    -heap  0x2000

    -stack 0x800

    -lrts6700.lib

     

                                                   

    /****************************************************************************/

    /*  Specify the Memory Configuration                                        */

    /****************************************************************************/

    /*TMS320C6727B : 256KB RAM, Base Address 0x10000000

    /*TMS320C6727B : 256KB ROM, Page 0, Base Address 0x00000000

    /*TMS320C6727B : 128 KB ROM, Page 1, Base Address 0x00040000

    /*SDRAM 128Mbits, 16MBytes: Base Address 0x80000000

    *****************************************************************************/

    MEMORY

    {

      ROM_VECS                                       : origin = 0x00000004 length = 0xffc

      ROM                                                    : origin = 0x00001000 length = 0x5EFFF

      VEC                                                      : origin = 0x10000000 length = 0x9FF

      VEC_RET                                            : origin = 0x10000A00 length = 0xFF

      PAR_LIST                                           : origin = 0x10000B00 length = 0x270

      LABEL                                                  : origin = 0x10000D74 length = 0x20

      RAM                                    : origin = 0x10000F00 length = 0x3E0E0

      INPUT_BUFFER_MEM                 : origin = 0x1003F000 length = 0x80

      OUTPUT_BUFFER_MEM : origin = 0x1003F100 length = 0x100

      SDRAM                                               : origin = 0x80000000 length = 0x1000000

     

    }

     

     

     

     

    /****************************************************************************/

    /*  Specify the Output Sections                                             */

    /****************************************************************************/

     

    SECTIONS

    {

                    SDRAM_BUFFER > SDRAM

                    INPUT_BUFFER > INPUT_BUFFER_MEM

                    OUTPUT_BUFFER > OUTPUT_BUFFER_MEM

                    FPGA_RAM > ROM_VECS

    }

     

    SECTIONS

    {

     

                    .boot_vectors  load = ROM_VECS

                    .parameter_list load = PAR_LIST

                    .vector                                  load = VEC

        .text                      load = RAM

        .stack          load = RAM

        .cinit          load = RAM

        .cio            load = RAM

        .const          load = RAM

        .data           load = RAM

        .switch         load = VEC

        .far            load = RAM

        .bss            load = RAM

        .sysmem         load = RAM

        .test_cache    load = RAM

       .pinit                   load = RAM  

        .packet         load = VEC_RET

        .err_buffers    load = RAM       

        .src_a_buffers  load = RAM    

        .src_b_buffers  load = RAM 

        .src_c_buffers  load = RAM    

        .src_d_buffers  load = RAM 

        .src_e_buffers  load = RAM    

        .src_f_buffers  load = RAM 

        .dst_buffers    load = RAM

      .dsp_data                          load = RAM

        .uhpitb_cmd     load = RAM

        .uhpitb_data    load = RAM

        .uhpitb_dst     load = RAM

        .src_buffers    load = RAM

    }

     

    I'm I missing something here? Thanks for your help.
    Derek

  • 0 in reply to Derek Rasugu
    TI__Guru**** 173310 points

    Derek said:
    Clearly the "unconfigured" addresses are well within the address range for this chip.



    Are they also within the address range specified with the ROMS directive passed to the hex converter?

    The most common reason for these warning messages is that the load address of those sections in the COFF file falls outside the memory range defined in the ROMS directive in the hex command file. Are you passing a command file as input to the hex converter? If so, check the ROMS directive to make sure the memory spans the desired range.

     

  • 0 in reply to AartiG
    Prodigy 130 points

    You nailed it on the head. Works like a charm. Much appreciated.

    Derek