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C11 Atomic operation tradeoff

Gabriel B
Intellectual 351 points
Other Parts Discussed in Thread: ARM-CGT

Hi,

I'm using the 2.1.3.LTS ARM TI compiler with the a TI RM46, using CCS 12.4.

I want to build a performance sensitive datastructure that needs to support multiple threads (FreeRTOS).
To my understanding, I have two options to guarantee atomicity:

1. Do like the TI Hercules FreeRTOS Port, that disable ISR to create "critical section" 

2. Use the C11 header `#include <atomic.h>`  (that seems to be supported the RM46 core: Cortex-R4F)

To better understand the tradeoffs between those choices, I would like to better understand how the C11 atomic works inside the ARM TI compiler:
Are the  Atomic Variables lock free ?
What are the cost of atomic operations when compare to disabling ISR ?

Best Regards,
Gabriel

  • 0
    TI__Guru**** 197036 points

    Hi Gabriel,

    I am forwarding your questions to TI compiler e2e forum. C11 atomic operations are supported by bother TI ARM-CGT compiler and TI ARM-Clang compiler. I don't know how the atomic operations work inside the compilers.

  • 0 in reply to QJ Wang
    Intellectual 351 points

    Hi QJ,

    As always, thanks for your answer.
    Maybe I'm confused, but I thought this was the e2e forum for the TI compiler (Code Composer Studio > Code Composer Studio forum).

    If it's not the case, where could find it? It doesn't appear on https://e2e.ti.com/ table of content.

    Best,
    Gabriel

  • 0 in reply to Gabriel B
    TI__Guru**** 197036 points

    Hi Gabriel,

    As ARM Cortex-R TRM says that the L1 memory (TCM on RM46) has an internal exclusive monitor. It is a two-state (open and exclusive) state machine that manages the load/store exclusive accesses.

    When a load-exclusive access (ldrex) is performed, the internal monitor exclusive monitor moves to the exclusive state. It moves back to the open state when a store exclusive access.

    The internal exclusive monitor holds exclusivity state for the Cortex-R4 processor only. Any store exclusive access performed when the state is open fails. If the state is exclusive, the access passes if it is to non-shared memory but, if it is to shared memory, the access must be performed as an exclusive using the L2 memory interface. Whether the shared store-exclusive access passes or fails depends on the state of an external exclusive monitor which can track accesses made by other processors in the system.

    Since RM46x has only one processor and one L1 memory, I am not very clear about the LDREX and STREX instructions on this device. Let me check how LDREX and STREX work with different MPU settings on RM46 

    The compiler expert told me that the atomic operations were not tested in multiple threads program.  

  • 0 in reply to QJ Wang
    TI__Guru**** 197036 points

    Hi Gabriel,

    I need more time for testing, and will let you know my test result by this Friday (Oct 13).

  • 0 in reply to QJ Wang
    Intellectual 351 points

    Thank you QJ.
    I'm looking forward to your update.

  • 0 in reply to Gabriel B
    TI__Guru**** 197036 points

    Thanks, I will 

  • +1 in reply to QJ Wang
    TI__Guru**** 197036 points

    Hi Gabriel,

    Tried to store a data to MCU TCM with atomic operation, the internal function _atomic_store() is called and the LDREXD and STREXD instructions are used to access the memory location (shared or non-shared in MPU settings).

  • 0 in reply to QJ Wang
    Intellectual 351 points

    Hi QJ ! 

    Thanks for your answer. If we access to LDREX and STREX we should be good to use atomics.
    Do have an idea how those instruction interacts with Interrupts and DMA ?
    I don't seems to find any resources about this topic.

    Regards,

    Gabriel

  • 0 in reply to Gabriel B
    TI__Guru**** 197036 points

    Hi Gabriel,

    I don't know how LDREX and STREX interacts with INT and DMA.

  • 0 in reply to QJ Wang
    Intellectual 351 points

    Hi QJ, 

    Thanks. Let me know if you find some documentation about the topic.

    Regards,
    Gabriel