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Original question:

How to set 'Sync group cores' in Debug server script for SMP debug

CCS global breakpoint trigger latency

Hari Nagalla
Mastermind 27080 points


How does CCS implement global break points for multicore debug? Does it use hardware CTI or SW implemented? For example on AM64, i have configured A53-0, A53-1 and R5F-0 as one one group with global breakpoints enabled. I wonder what is the latency for the breakpoint trigger latency between the cores? for example A53-0 has hit a breakpoint, how long would it take for the R5F in the group to halt on this global breakpoint?

Thanks

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    TI__Guru**** 472411 points
    Hari Nagalla said:
    I wonder what is the latency for the breakpoint trigger latency between the cores? for example A53-0 has hit a breakpoint, how long would it take for the R5F in the group to halt on this global breakpoint?

    Global breakpoints are triggered by special debug logic on the device. Hence this latency can vary depending on the device. I will bring this thread to the attention of the device experts.

    Thanks

    ki