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Placement failure for object, but there is enough space, CCSv4

I get this error:

error: run placement fails for object ".cio", size 0x120 (page 0). Available ranges:

RAMM01   size: 0x7b0    unused: 0x130     max hole: 0x130

How to solve this problem? Is it a bug? I am running CCS version 4.2.3.00004

Also, should not .cio be placed in data memory meaning onto page 1 (not 0, as it is noted in the error) (RAMM01 is defined in page 1 section)? Thx.

  • What seems to be happening here is that the .cio section is treated as a "blocked" section. This means that the section needs to either fit completely within a page or begin at a page boundary. The codegen tools do this to optimize the data page (DP) register load. In your case, the size of the .cio section is 0x120 and even though 0x130 is unused in memory, since the section gets moved to start at the next page boundary there is not enough space to fit the section.

    A related forum post for reference is: http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/p/21702/83828.aspx#83828

    This FAQ also covers this topic: http://processors.wiki.ti.com/index.php/C28x_Compiler_-_Understanding_Linking#Q:_The_linker_says_.22placement_fails_for_object.22_but_the_available_memory_is_larger_than_the_section

     

    Slavica Golijanin said:
    Also, should not .cio be placed in data memory meaning onto page 1 (not 0, as it is noted in the error) (RAMM01 is defined in page 1 section)?

    It depends on how it is allocated in the linker command file as this is within user control. In general, it is recommended that.cio be placed in Page1.

  • I forgot to say that the application includes SYS BIOS v 6.30.03.46 if that makes any difference. 

    I've got the program compile (changed memory mapping - defined all sections in RTSC package and did all sections mapping in .cfg file), but I still have some questions related to your response:

    1. How is RAM devided into pages? What is the page size for F28035 - I could not find it in the documentation nor on-line.

    2. You said a section allocation is within user control. Agree. But the linker command explicitly noted the .cio was supposed to be placed on page 1 and the linker would still try to place it on page 0.

    PAGE 1 :

     

    RAMM01 :

    origin = 0x000050, length = 0x0007B0

    and

    SECTIONS { .cio     : > RAMM01    PAGE = 1 }

    What am I missing? The linker places RAMM01 on page 1 in an application without SYS BIOS.

    3. Since SYS BIOS is part of the application I had to create RTSC package with the memory mapping and all sections were properly marked as being code, data or code/data spaces. However all data spaces end up on PAGE 0 (got this from the map file). How can I force data sections to end up on PAGE 1?

    Thanks.

  • Slavica Golijanin said:
    1. How is RAM devided into pages? What is the page size for F28035 - I could not find it in the documentation nor on-line.

    This is in reference to 64-word data pages that are accessed as offsets from the DP register.  See section 5.1 of the C28x CPU Reference Guide.  The compiler arranges for sections like .cio to be blocked so that it can know, in relative terms, where the DP address boundaries lie.  Such blocking limits where a section may be placed in memory.  Even though enough space may be available, that space is not blocked as the compiler requested, and so cannot be used.

    Also note these 64-word pages are not related to the PAGE 0 for code and PAGE 1 for data you use in the link command file.  It is easily confused, since the word page is used in both contexts.  But they are different.

    I don't think this clears up everything, but it should help.  Your remaining questions seem related to your RTSC configuration.  If this post doesn't help you figure that out, I recommend you post your next set of questions to the BIOS forum.

    Thanks and regards,

    -George

  • Thank you George. Yes, this sorts out the pages I was wondering about. I will wait a bit if anyone responds to my RTSC configuration questions before posting them to the BIOS forum, because they are somewhat related to the compiler/linker.

    Thanks,

    Slavica