Hi,
I'm trying to generate a .bin file from the CCSv4 .out because I wrote a can bootloader and need a bin file to progrma my application file. I read the CCS4 wiki and I modified the postbuild script provideded to use C2000 .exe files in these way.
"${CCE_INSTALL_ROOT}/utils/tiobj2bin/tiobj2bin.bat" "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin" "${CG_TOOL_ROOT}/bin/ofd2000.exe" "${CG_TOOL_ROOT}/bin/hex2000.exe" "${CCE_INSTALL_ROOT}/utils/tiobj2bin/mkhex4bin.exe"
but I got an error from the postbuild:
'Finished building target: SUNSYS-WUDR.out'
' '
C:/Program Files/Texas Instruments/ccsv4/utils/gmake/gmake --no-print-directory post-build
"C:/Program Files/Texas Instruments/ccsv4/utils/tiobj2bin/tiobj2bin.bat" "SUNSYS-WUDR.out" "SUNSYS-WUDR.bin" "C:/Program Files/Texas Instruments/ccsv4/tools/compiler/c2000/bin/ofd2000.exe" "C:/Program Files/Texas Instruments/ccsv4/tools/compiler/c2000/bin/hex2000.exe" -i "C:/Program Files/Texas Instruments/ccsv4/utils/tiobj2bin/mkhex4bin.exe"
Unknown option: i
warning: section SUNSYS-WUDR.out(ramfuncs) at 07e0000h falls in unconfigured
memory (skipped)
warning: section SUNSYS-WUDR.out(.text) at 07e0d20h falls in unconfigured
memory (skipped)
warning: section SUNSYS-WUDR.out(.econst) at 07e5b34h falls in unconfigured
memory (skipped)
warning: section SUNSYS-WUDR.out(.cinit) at 07e6910h falls in unconfigured
memory (skipped)
warning: section SUNSYS-WUDR.out(IQmath) at 07e6d68h falls in unconfigured
memory (skipped)
warning: section SUNSYS-WUDR.out(codestart) at 07e6f6ah falls in unconfigured
memory (skipped)
The memory locations in the warning are completely out from my cmd file.
I don't know if I'm using the correct script or not.
thanks
Michele
/*
// TI File $Revision: /main/1 $
// Checkin $Date: November 9, 2009 15:08:03 $
//###########################################################################
//
// FILE: F28031.cmd
//
// TITLE: Linker Command File For F28031 Device
//
//###########################################################################
// $TI Release: 2803x C/C++ Header Files and Peripheral Examples V1.24 $
// $Release Date: January 11, 2011 $
//###########################################################################
*/
/* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in <base>\DSP2803x_Headers\cmd // // For BIOS applications add: DSP2803x_Headers_BIOS.cmd // For nonBIOS applications add: DSP2803x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l DSP2803x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l DSP2803x_Headers_BIOS.cmd */ /* 2) In your project add the path to <base>\DSP2803x_headers\cmd to the library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F28031 PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F2803x are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. L0 memory block is mirrored - that is it can be accessed in high memory or low memory. For simplicity only one instance is used in this linker file. Contiguous SARAM memory blocks or flash sectors can be be combined if required to create a larger memory block. */
/*FLASHF : origin = 0x3F2000, length = 0x001000*/ /* on-chip FLASH */
/*FLASHE : origin = 0x3F3000, length = 0x001000*/ /* on-chip FLASH */
/*FLASHD : origin = 0x3F4000, length = 0x001000*/ /* on-chip FLASH */
/*FLASHC : origin = 0x3F5000, length = 0x001000*/ /* on-chip FLASH */
/*FLASHB : origin = 0x3F6000, length = 0x001000*/ /* on-chip FLASH */
/*FLASHA : origin = 0x3F7000, length = 0x000F80*/ /* on-chip FLASH */
/*RAML0 : origin = 0x008000, length = 0x000800*/ /* on-chip RAM block L0 */
/*RAML1 : origin = 0x008800, length = 0x000400*/ /* on-chip RAM block L1 */
/*RAML2 : origin = 0x008C00, length = 0x000400*/ /* on-chip RAM block L2 */
/*RAML3 : origin = 0x009000, length = 0x000800*/ /* on-chip RAM block L3 */
/*FLASHH : origin = 0x3F0000, length = 0x001000*/ /* on-chip FLASH */
/*FLASHG : origin = 0x3F1000, length = 0x001000*/ /* on-chip FLASH */
/*RAMM0 : origin = 0x000050, length = 0x0003B0*/ /* on-chip RAM block M0 */
/*RAMM1 : origin = 0x000400, length = 0x000400*/ /* on-chip RAM block M1 */
-stack=0x100 -heap=0x50 MEMORY { PAGE
0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAMLP :
origin = 0x008000, length = 0x000C00 /* on-chip RAM block L0 L1 */
OTP :
origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHP :
origin = 0x3F2000, length = 0x005F80 /* on-chip FLASHA-B-C-D-E-F */
CSM_RSVD :
origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN :
origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 :
origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES :
origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 :
origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 :
origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM :
origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET :
origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS :
origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
/* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD :
origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM :
origin = 0x000050, length = 0x0007B0 /* on-chip RAM block M0 M1 */
RAMLD :
origin = 0x008C00, length = 0x000C00 /* on-chip RAM block L2 L3 */
FLASHD :
origin = 0x3F0000, length = 0x002000 /* on-chip FLASHH FLASHG */
} /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS {
/* Allocate program areas: */
.cinit : > FLASHP PAGE = 0
.pinit : > FLASHP, PAGE = 0
.text : > FLASHP PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs :
LOAD = FLASHP,
RUN = RAMLP,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM PAGE = 1
.ebss : > RAMLD PAGE = 1
.esysmem : > RAMLD PAGE = 1
.cio : > RAMLD PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHP PAGE = 0
.switch : > FLASHP PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHP PAGE = 0
/* Math Code */
IQmathTables : > IQTABLES, PAGE = 0,
TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam) } */
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam) } */
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0,
TYPE = DSECT
}
/* //=========================================================================== // End of file. //=========================================================================== */
