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Opfield length and position

Anonymous
Anonymous


Hi,

 

I would like to ask a question on opcode.

 

I noticed that opfield on C64x are of varied length, and are at different position within opcode.

 

 

In instructions above, opfield's lengths are 7, 5, and 3 bits; their starting bit are 5th, 6th and 4th bit.

http://en.wikipedia.org/wiki/Opcode said:

In computer science, an opcode (operation code) is the portion of a machine language instruction that specifies the operation to be performed. Their specification and format are laid out in the instruction set architecture of the processor in question (which may be a general CPU or a more specialized processing unit). Apart from the opcode itself, an instruction normally also has one or more specifiers for operands (i.e. data) on which the operation should act, although some operations may have implicit operands, or none at all. There are instruction sets with nearly uniform fields for opcode and operand specifiers, as well as others (the x86 architecture for instance) with a more complicated, varied length structure. [1]

From the above observation C64x is obviously of varied opfield design. In execution, how does the CPU know where within each 32bit opcode to find the opfield?

 

Zheng

 

 

  • 0
    TI__Guru**** 251270 points

    Zheng Zhao said:
    how does the CPU know where within each 32bit opcode to find the opfield?

    No one who watches this forum has that much knowledge of CPU design.  It seems likely the CPU instruction decode HW looks at the first few bits of the opcode, and based on what it finds there, decides how to interpret the rest.  That process may repeat a few times before an instruction is fully decoded.

    Thanks and regards,

    -George

     

  • 0
    TI__Expert 4930 points

    Note that you can also interpret it as a fixed field from bits 2 to 12.  Some of the bits are constant or don't-care in the instructions you cited, and the presentation chose to discuss only the parts that vary among the set of actual instructions grouped under the name.

  • Anonymous
    0 Anonymous in reply to pf

    George,

    If from bit 2 to 12, the bit 12 in the first table row (CMPLT) is cross path usage indication, same in 2nd table row, but part of mode in 3rd row.

    In addition, bits between OP and the LST s and p are also of varied length.

    I choose to accept your comment that this belong to CPU design domain, and do not attempt to probe further.

     

    Zheng

     

  • Anonymous
    0 Anonymous in reply to pf

    pf,

    I didn't look carefully at the name and thought the post was from George just now, sorry.

    Do you have knowledge on how varied length opcode are decoded? Is it as perhaps in an iterative way as George outlined?

     

    Zheng