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Porting content of GEL file to C code

Eric Chen
Intellectual 810 points

Other Parts Discussed in Thread: SYSBIOS

Hi,

    I transferred the initialization code of GEL to my C code source. When I ran the code, exception occurred and error message as the following:

[CortexA8] Exception occurred in ThreadType_Main.
Main handle: 0x0.
Main stack base: 0x8001bddc.
Main stack size: 0x1000.
R0 = 0x481c5294  R8  = 0x4031cfcc
R1 = 0x00000000  R9  = 0x4031cff4
R2 = 0x00000013  R10 = 0x00027c94
R3 = 0x0000029a  R11 = 0x00027c94
R4 = 0x48[CortexA8] 1c3000  R12 = 0x481c5294
R5 = 0x50000000  SP(R13) = 0x8001cd48
R6 = 0x00000001  LR(R14) = 0x80000194
R7 = 0x00000000  PC(R15) = 0x80000038
PSR = 0x6000019f
ti.sysbios.family.arm.exc.Exception: line 174: E_dataAbort: pc = 0x80000038, lr = 0x80000194.
xdc.ru[CortexA8] ntime.Error.raise: terminating execution

 

My initialization sequence from GEL file is as the following:

        DDR_PLL_Config();
        cmd_DDR2_EMIF0_EMIF1_Config(DDR2_PHY_RD_DQS_CS0_DEFINE,DDR2_PHY_WR_DQS_CS0_DEFINE,
        DDR2_PHY_FIFO_WE_CS0_DEFINE,DDR2_PHY_WR_DATA_CS0_DEFINE,DDR2_EMIF_READ_LATENCY_DEFINE,
        DDR2_EMIF_TIM1_DEFINE,DDR2_EMIF_TIM2_DEFINE,DDR2_EMIF_TIM3_DEFINE,
        DDR2_EMIF_REF_CTRL_DEFINE,DDR2_EMIF_SDRAM_CONFIG_DEFINE);

        UARTClkEnable();
        //
        SPI_Enable();
        //
        GPMC_ClkEnable();
        //
        I2C0Enable();
        //
        SpinboxEnable();
        //       
        MaiboxEnable();
        //
        ////Timer0_32kHClkEnable();
        Timer1_32kHClkEnable();
        Timer2_32kHClkEnable();
        Timer3_32kHClkEnable();
        Timer4_32kHClkEnable();
        Timer5_32kHClkEnable();
        Timer6_32kHClkEnable();
        Timer7_32kHClkEnable();

        Could any one help to advice what's wrong with those codes? thanks.

 

Regards,

    Eric

  • 0
    TI__Guru**** 478571 points

    Hi Eric,

    What device are you using? And from where is this application being run (what memory on the target)?

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 810 points

    Hi Ki,

        I'm using TI8148 and load my code in external DDR2 memory.

        The environment is CCS 5.1 in Windows XP. It first executes what GEL file would do in my code when it's launch.

     

        Here are my operating steps:

    1. In CCS, launch target configuration then connect target cortex A8.

    2. Load GEL file to initialize DDR2 relative registers (PLL, PRCM, PHY, VTP, etc)

    3. At this stage, check that 0x80000000 (starting addr of DDR2 memory) and 0x481C5294 (DDR PLL control) are accessible in memory browser.

    4. Load my code (to DDR2 memory).

    5. Run my code. The exception would occurred while accessing 0x481C5294 which is the first register to be accessed.

     

        I notice that after I load my code in step 4, the area of 0x481c5### becomes un-accessible.

     

        If I remark the code which ported from GEL file and initialize by GEL file, it could be executed successfully.