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UCD3138: a quenstion about current share

liwei qi
Expert 1160 points
Part Number: UCD3138

Tool/software:

Ch1: input current 1 from one module ch2:input current 2 from another module ch3:debug_io ch4:vout

In the state machine of  ramp up, the debug_io will be change to high when enable current share function. The output voltage will be shock. The cause is that the register of  FeCtrl0Regs.EADCDAC.bit.DAC_DITHER_EN is enabled. How can I solve this issue? why?

  • 0
    TI__Expert 8580 points

    Hello Liwei,

    What topology are you using? Also, what is the debug_io signal? Is this a signal that turns on when the current sharing is enabled? 

    "The output voltage will be shock." Can you please elaborate on this statement? Does this mean that the Vout is shorted?

    I do not understand how the FeCtrl0Regs.EADCDAC.bit.DAC_DITHER_EN register causes this issue. Enabling this register just means you are enabling front end dithering. Do you not want to use dithering?

    Regards,

    Jonathan Wong

  • 0 in reply to Jonathan Wong
    Expert 1160 points

    HI,Jonathan Wong:

         Te topology is HSFB. The debug_io signal is for debug that in the statamchine of idle is low and it will be change high when the current sharing is enable. you can see the picture that the output will be become low when the debug_io change to high. 

        Yes. i want to use dithering function for current share. Since the output impedance of a power supply can be as low as a fraction of milli-Ohm; a very small change in the output voltage will cause a substantial change in the output current. Therefore the DAC dithering feature needs to be turned on.

        I refer to the LLC firmware about the current share function. I don't know why the output voltage droop after enable the function of dithering .

  • 0 in reply to liwei qi
    TI__Expert 8580 points

    Hello Liwei,

    Yes, I believe dithering is an important feature to include. However, in your original post, you said "The cause is that the register of  FeCtrl0Regs.EADCDAC.bit.DAC_DITHER_EN is enabled." Why do you think this register is the cause of the current sharing issue?

    Can you please share:

    • The schematic
    • The current sharing code snippet
    • Magnitude of voltage droop (oscope shows ~1V droop on 8V output. Please confirm actual values)
    • Magnitude of current share droop (oscope shows ~2.5A droop on 2.5A output. Please confirm actual values)
      • Are you seeing negative current during the droop?

    You can also try using a debug signal that occurs in your state machine during the transition between current share disable --> current share enable. Then, we can see how long it takes for the UCD to execute the current sharing code. 

    Regards,

    Jonathan Wong

  • 0 in reply to Jonathan Wong
    Expert 1160 points

    Hi,Jonathan Wong:

            I have found the reason of the issue.Thank you very much! 

  • 0 in reply to liwei qi
    TI__Expert 8580 points

    Hello Liwei,

    Glad your system is working properly. May I ask what the solution to the issue was?

    Regards,

    Jonathan Wong