• Locked Locked
  • Replies 1 reply
  • Subscribers 52 subscribers
  • Views 295 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

One core out of 4 hangs in-between c_int00 and main

Lidwine Martinot
Prodigy 30 points


Hi,

I load the same .out file on 4 cores and one of them hangs before reaching the main. I noticed in the map file the following:

1) The L2SRAM section at the top of the map file is:

         name            origin    length      used     unused   attr    fill

----------------------  --------  ---------  --------  --------  ----  --------

  L2SRAM                00800000   00100000  000d2de4  0002d21c  RW X

 

2) In the detailed section of the map:

 If I look at the last element in L2SRAM, .cinit, I have:

 

run origin  load origin   length   init length attrs members

----------  ----------- ---------- ----------- ----- -------

008cd198    008cd198    00005d6c   00005d6c    r--

  008cd198    008cd198    00005d6c   00005d6c    r-- .cinit

 

If we look at the address of the last element in .cinit: (008cd198   + 00005d6c  ) = 8d2f04 

it is more than the above L2SRAM start address plus used (00800000 + 000d2de4)

- Why?

- Is that an issue?

-Could that explain that the code hangs in _c_int00 prior reaching main ?

-Why do I have this behavior on core 0 only when the same code is executed on the 4 cores prior the main?

Thank you for your help

  • TI__Guru**** 173310 points

    Lidwine,

    Sorry about the delayed reply to this post, it seems to have fallen through the cracks. Are you still experiencing this issue?

    In general, problems with code not reaching main could be due to many reasons and can be difficult to troubleshoot, but I will try to provide some suggestions and references. Some of the reasons for such issues are hardware not properly configured, initialization hangs at some point or the initialization code has problems.

    Which device/board are you working with? Are you using the appropriate GEL file for that board?
    And what version of CCS?

    It is odd that the link map file lists the .cinit section to fall outside the L2SRAM region but that could happen if the linker command file is set up to split .cinit between L2SRAM and the adjoining memory region. Further inspection of the linker command file and link map file should explain if this is valid or not.

    Have you tried setting your program to halt at c_int00 and then stepped through the code or run the code to see where it hangs?  

    Here is a thread that might have some additional ideas for troubleshooting (although it does not explicitly deal with a multi-core device):
    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/136216.aspx

    Also another thread that uses a RTSC program: http://e2e.ti.com/support/embedded/bios/f/355/t/162113.aspx