TMS570LS1227: GIO

Hi Sebastian,

Hi Sebastian,

Sebastian Mazur said:

when I set Output 5 to a high state (1), it appears that other registers are being modified unexpectedly.

I can see the changing registers are DIn, DOut, DSet and DClr. 

This is expected only. Because gioSetBit API usually write into the DSET register like as shown below:

And when we write 1 to this register then this will make corresponding pin value to high right, when this happened obviously Din pin value becomes-1, because this register read the whatever value present on the pin.

And similarly, Dout register value also becomes 1 because this register also used to change the pin output state directly. So whenver any change in the pin output state value then this will also reflect the same state.

Similarly if you write 1 to the DClr register and this will change register values like below.

Now the pin state is 0 right so all the registers like DIn, DOut, DSet and DClr produces 0 on the corresponding bits like as shown below.

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Thanks & regards,
Jagadish.

Thank you for your response.

I’m facing an issue when setting gio5 to 1.
Ideally, this should set the pin to a high state, correct?
However, as observed on my analyzer, the signal remains high only momentarily before reverting back to low.
Could you please help clarify the following points:

1) Why does the DClr signal switch to high when I set DSet to high? Aren't these two independent signals?
2) How can I configure the gio5 pin to remain in a permanent high state?

Hi,

Which board you are using? Is TI board or custom board?

If it is TI, then exactly which board you are using? Launchpad or HDK?

I am using TI board: TMS570LS12x Hercules Development Kit (HDK).

Sebastian Mazur said:

I am using TI board: TMS570LS12x Hercules Development Kit (HDK).

Thanks for the confirmation.

Sebastian Mazur said:

1) Why does the DClr signal switch to high when I set DSet to high? Aren't these two independent signals?

Are you measuring your signal at right pin? GIO_A5 is at 23rd pin of J11 connector.

Make sure to measure at right signal, because i don't see any other reason for wrong waveform. Unfortunately, i don't have this board to test issue at my end.

If above suggestion doesn't help you then could you please setup one live debugging session?

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Thanks & regards,
Jagadish.

I have verified the connections: Pin 23 (GIOA[5]) and Pin 35 (GND).
Could you confirm whether there is a direct relationship where DClr is automatically set to 1 when DSet is set to 1?
I still don't understand why DClr (which is to clear gio) is changing.

Hi Sebastian,

Sebastian Mazur said:

Could you confirm whether there is a direct relationship where DClr is automatically set to 1 when DSet is set to 1?

This is expected behavior only.

If you verify DClr or DSet register definitions in TRM there you can find a note like below.

Note: The current logic state of the GIODOUT bit will also be displayed by this bit.

So, this means DClr and DSet registers also implies the status of GIODOUT that means they will directly imply the status of the output pin.

That means if you change the pin status the corresponding new status can be read back from these registers as well. 

For example, if you set the output pin to logic high using DSet register, then after that the corresponding output status that is logic high will also reflect on DSet and DClr registers along with DOut register.

Similarly, if you clear the output pin to logic low using DClr register (writing 1 to the bit), then after that the corresponding output status that is logic low will also reflect on DSet and DClr registers along with DOut register.

So, this behavior of DSet and DClr is not the issue, the root cause should be something else, some hardware issue. I am suspecting there should be some short between pin with GND. So this is the reason even if we write logic high it is slowly pulling to logic low.

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Thanks & regards,
Jagadish.