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AM2634-Q1: Core 0-1 is not started

K sai
Prodigy 10 points

Part Number: AM2634-Q1

Hi Ti team, 

we are developing application which core 0-0 and core 0-1 involved. Core 0-0 is responsible for application and core 0-1 responsible for the ethernet communication. The core 0-0 and core 0-1 is communication via safeIPC/notify IPC. We have prvided enough memory (OCRAM) for the both cores and we feel no memory overlap between them. 

Issue:

when increasing the code of core 0-0 causes core 0-1 operation which means core 0-0 is working normal and core 0-1 is not at all running (i.e, we are printing the caracter after driversInit()). we have changed OCRAM start address and reduce the code size of core 0-0 but no use. 

Questions:

1.Is any specific configuration shall follow to be use the core 0-0 and core 0-1?

2. What size of OCRAM can be used?

3. is SBL in OCRAM is OK are not ? if it is required what should be address of this?

4. in core 0-1 has the CPPI_DESC memory, where it can keep in OCRAM?

5. what should be minimum size of the OCRAM?

6. what size of OCRAM shall fix for OCRAM and should we keep any free space on OCRAM?

7. is any specific valus of stack and heep size shall followed?

Attachments: 

Herewith we are attaching the images of our configuration and memory details. Kindly help us to come out of the issue...

core 0-0- syscfg

linker.cmd:

core 0-0

MEMORY
{
    R5F_VECS   : ORIGIN = 0x0 , LENGTH = 0x40 
    R5F_TCMA   : ORIGIN = 0x40 , LENGTH = 0x7FC0 
    R5F_TCMB   : ORIGIN = 0x80000 , LENGTH = 0x8000 
    SBL   : ORIGIN = 0x60000000 , LENGTH = 0x40000 
    OCRAM   : ORIGIN = 0x70040000 , LENGTH = 0x80000
    USER_SHM_MEM   : ORIGIN = 0x701D0000 , LENGTH = 0x4000 
    LOG_SHM_MEM   : ORIGIN = 0x701D4000 , LENGTH = 0x4000 
    FLASH   : ORIGIN = 0x60100000 , LENGTH = 0x80000 
    RTOS_NORTOS_IPC_SHM_MEM   : ORIGIN = 0x72000000 , LENGTH = 0x3E80 
    MAILBOX_HSM   : ORIGIN = 0x44000000 , LENGTH = 0x3CE 
    MAILBOX_R5F   : ORIGIN = 0x44000400 , LENGTH = 0x3CE 

    /* For memory Regions not defined in this core but shared by other cores with the current core */

}

core 0-1:

MEMORY
{
    R5F_VECS   : ORIGIN = 0x0 , LENGTH = 0x40 
    R5F_TCMA   : ORIGIN = 0x40 , LENGTH = 0x7FC0 
    R5F_TCMB   : ORIGIN = 0x80000 , LENGTH = 0x8000 
    OCRAM   : ORIGIN = 0x700C5000 , LENGTH = 0xF0000 
    CPPI_DESC   : ORIGIN = 0x70000000 , LENGTH = 0x4000 
    FLASH   : ORIGIN = 0x60180000 , LENGTH = 0x80000 

    /* For memory Regions not defined in this core but shared by other cores with the current core */

    USER_SHM_MEM   : ORIGIN = 0x701D0000 , LENGTH = 0x4000  
    LOG_SHM_MEM   : ORIGIN = 0x701D4000 , LENGTH = 0x4000  
    RTOS_NORTOS_IPC_SHM_MEM   : ORIGIN = 0x72000000 , LENGTH = 0x3E80  
    MAILBOX_HSM   : ORIGIN = 0x44000000 , LENGTH = 0x3CE  
    MAILBOX_R5F   : ORIGIN = 0x44000400 , LENGTH = 0x3CE  

}

 

find below core 0-0 syscfg

image.png

 

find below core 0-1 syscfg

image.png

 

  • 0
    TI__Expert 5635 points

    Hi,

    Apologies for the delay in response.

    K sai said:

    Is any specific configuration shall follow to be use the core 0-0 and core 0-1?

    The device should be in split core mode. As the code is running this would be done. Other than that, there are no specific requirements

    Please see the multicore example from the SDK to see if there are some configuration differences in your case.

    K sai said:
    What size of OCRAM can be used?

    This depends on the size of the code that is preset in each core. This is the OCRAM map for AM263

    Starting Address: 0x7000 0000

    Ending Address: 0x701F FFFF

    Length: 2 MB

    K sai said:

    is SBL in OCRAM is OK are not ? if it is required what should be address of this?

    This is okay. The address that is reserved in the SDK examples can be used for SBL.

    Question: By address do you mean the address where SBL should be present in flash or the address which it should use to execute?

    K sai said:
    in core 0-1 has the CPPI_DESC memory, where it can keep in OCRAM?

    It can be kept anywhere in OCRAM. But it should be Non-cached.

    K sai said:
    what should be minimum size of the OCRAM?

    Question: By minimum do you mean the least possible OCRAM size that can be allocated?

    K sai said:
    what size of OCRAM shall fix for OCRAM and should we keep any free space on OCRAM?

    Free space in OCRAM would not be required. Unused memory addresses will remain unused. 

    K sai said:
    is any specific valus of stack and heep size shall followed?

    This depends on your application requirements.

    In the failure scenario,

    - What are you seeing on core0-1. Has the code hit some exceptions?

    - Is it possible to run code 0-1 individually. In that case, what is the observation? 

    Thanks & Regards,

    Aswin

  • 0
    TI__Expert 5635 points

    Hi,

    Also, is it possible to share the map file of both the cores? This would help me to better understand how the code is organized.

    Thanks & Regards,

    Aswin