Part Number: AM2434
Hi,
I am working on a multicore application using the AM2434 (FreeRTOS) and am running into a hardware exception regarding atomic memory accesses.
The Architecture:
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Core-1 (Server): Writes a 64-bit variable to a shared MSRAM region.
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Other Cores (Clients): Constantly polling/reading this exact same 64-bit memory address.
The Memory Configuration: The shared MSRAM region is configured in the MPU with the following attributes:
Memory Type: Normal
Cache Policy: Non-Cacheable, Non-Bufferable (TEX=001, C=0, B=0)
Shareability: Shareable (S=1)
Permissions: Supervisor RW, User RW, Execute Never
The Problem: To prevent torn reads across the cores, I am using the standard ATOMIC_STORE macro for the 64-bit write. The compiler correctly generates the ldrexd and strexd instructions.
However, when stepping through the disassembly in Code Composer Studio, the CPU throws a Data Abort exception the exact moment it tries to execute the ldrexd command on this shared memory pointer.
My Questions:
1.Does the AM2434 interconnect/AXI bus support the Global Exclusive Monitor for the shared MSRAM region to allow ldrexd/strexd instructions?
2.If the Exclusive Monitor is not supported here, what is the recommended TI solution for locking shared memory or safely passing 64-bit variables between cores without torn reads?
Thanks,
Regards,
Eli
