TMS320C6747: C6x compiler barrier

Part Number: TMS320C6747

Hello,

I am trying to implement a queue for our project using the TMS320C6747 DSP. We are using SYS/BIOS and the queue is used to communicate between Tasks as well as between Task and Hwi.

The Compiler is CGT C6000 v8.3.13. I need some clarification on the following section from the compiler's user guide (SPRUI04D, www.ti.com/.../sprui04g.pdf

Section 8.6.9 Using Intrinsics for Interrupt Control and Atomic Sections contains the following code example and says:

These intrinsics [_disable_interrupts(), _enable_interrupts( )] provide a barrier to optimization and are therefore appropriate for implementing a critical (or atomic) section.

unsigned int restore_value;
restore_value = _disable_interrupts();
if (sem) sem--;
_restore_interrupts(restore_value);

The variable name `sem` used in the example implies some form of semaphore. My question is about the code surrounding the critical section:
Are all memory writes that appear before the call to _disable_interrupts() in source code guaranteed to be emitted before the call to _disable_interrupts() in the compiled binary? I could not find this guarantee inside the user guide.

Context:
We need to set a flag inside the critical section to signal that new data is available. But obviously the data has to be written to memory first. If the compiler reorders the memory write to after the critical section, the program would break. I would prefer not to move the memory write of the data inside the critical section, because the data is quite large.

Thank you very much for your support.

  • Hello Tim,

    Please note that we can no longer answer software design questions about C674x devices on the e2e forums, as per the limited support banner on the product page:
    https://www.ti.com/product/TMS320C6747

    I am reassigning your thread to see if we can find someone familiar with the C6x compiler user guide. If you don't get a response in a few business days, feel free to ping the thread to see if we can provide any additional information about that document's code example.

    Regards,

    Nick

  • Those intrinsics are special intrinsics in the compiler that should prevent the compiler from reordering memory writes across either of __disable_interrupts and __restore_interrupts. Let us know if that doesn't happen.

  • Thanks for your answer, this is what I was looking for.

  • Thank you for reassigning the thread! I haven't noticed the limited support banner on the product page before but this is good to know.

  • Final thoughts on part selection

    If you have the in-house expertise to do your design on C674x with the old SYS/BIOS software, go for it! Our ability to produce this part in our factories is unrelated to the support team's ability to answer software questions.

    This part status is "active", as per the product page. You can find more information about the product life cyle here:
    https://www.ti.com/quality-reliability/quality/product-life-cycle.html

    but to summarize: as long as people are buying a part, and as long as we can keep producing it, we WILL keep producing it. So from a supply chain standpoint, you are safe to use C674x in your design. There are so many C674x products out there I wouldn't be surprised if this part keeps being manufactured for another 20+ years.

    If your company would need design support, or if you want more "modern" software which is still getting bugfixes, then it may be a good idea to evaluate other processors. If that is the case, feel free to reach out to your TI representative or create a new e2e thread to discuss other options.

    Regards,

    Nick