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C6000 compiler: why does XDC forces loadable (.rodata) and zero-fill (.bss) into same segment.

Other Parts Discussed in Thread: 4430

We are writing an ELF loader for C64T EABI binaries compiled with TI_CGT_C6000_7.3.2.

In the XDC  for the C64T on the OMAP 4430, xdctools_3_23_00_32/packages/ti/targets/elf/linkUtils.xs requires that .rodata, .bss and .neardata be in the same segment.

                if(!(bssAlloc == nearAlloc && bssAlloc == roAlloc)) {
                    throw new Error("Allocations for sections '.bss', '.rodata'"
                        + " and '.neardata' must be same.");
                }

This is "odd" because a vanilla ELF loader would zero-fill initialize (not load from image) the .bss section.  Is there a reason why XDC is enforcing a "rule" such that zero-fill .bss is forced into an initialized segment?

Is there a reason why XDC precludes placing .rodata into a read-only segment (by means of AMMU configuration)?  Requiring .rodata section into a read-write segment would needlessly expose it to errant writes.

The output of elf/linkUtils.xs produces a linker file with a SECTIONS group with all three sections:

GROUP: load > LOAD_RW { .bss: .neardata: .rodata: }

There is some mention in "C6000 EABI Application Report" section 13.4.4 referring to DSBT, but DSBT option to C6000 compiler is for dynamic loading only... 

Obviously, there is some reason for forced combining of bss/rodata/neardata, please help us understand the issue.

Thanks in advance.

dave

  • The data the compiler places in the sections .neardata, .rodata, and .bss are all accessed with DP-relative addressing mode.  That is, some fixed offset encoded in the instruction is added to the DP register to form the address of the data.  Thus, these sections must be allocated next to each other.

    Thanks and regards,

    -George