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A problem of Profiling in CCS3.3

lijie Wang
Prodigy 230 points

Other Parts Discussed in Thread: TMS320DM642

Hello, I have a problem in profiling with CCS3.3.

My platform environment  is as the following roughly:

CCS3.3 +  Cycle Simulation + TMS320DM642 little Endianness.

Profiling setup activities : Collect Application Level Profile for Total Cycles and Code Size;  Collect Data on Cache Accesses Over a Specific Address Range;  Collect Cache Information over time.

I  control the Profiling to collect  the data information during  a part of  my  program.

From the Profiling->Viewer,  the total cycles is  2648684313. From the Profiling->Tuning->CacheTune , I can see the graph of data cache and program cache. 

But the problem occurs.  The X-axis of the graph  can only display  the information of 250 cycles.(just  like the picture added).

Why it only display 0~250 cycles?  The total cycles exceed the range the profiling component can display?

And the Trace Information of the graph display like:

Anybody also met  this problem? 

Anybody could help me ?  Thank you very much! 

  • 0
    TI__Guru**** 483141 points

    Hello,

    I have to recommend against using the CacheTune Tool. The information given by the tool is not always reliable and support for it was dropped long ago (even when CCSv3 was still supported). Sorry.

    ki

  • 0 in reply to Ki
    Prodigy 230 points

    Hi Lee,

    Thank you for you advises.

    I want to collect the cache information in the Simulation. Such as Total cycles, cache hit rate, when and where the cache misses occur. And How many data will be accessed from the SDRAM in each cache miss.

    In your opinion, which Tool  could I use to collect these data?  I think there must be some tools could collect the reliable information in CCS3.3 or later version.

    Thanks. I'm looking forward to your reply.

  • 0 in reply to Ki
    Prodigy 230 points

    Could you give me some advise of my problem?

    I feel very anxious with it.

    Thanks!

  • 0 in reply to lijie Wang
    TI__Guru**** 483141 points

    Hi Lijie,

    Both the CCS profiler and the profile clock can count many of those events you are looking for. It sounds like you already have used the CCS profiler to collect cycle counts. You can also use it to collect cache information and other events. I would continue to use the CCS profiler.

    Thanks

    ki

  • 0 in reply to Ki
    Prodigy 230 points

    Hi, ki

    Thank you for your advises. Yes, I have used the CCS profiler to collect cycle counts and cache information.Such as Total cycles, cache hit rate.

    But I want to find out when and where the cache miss occurs and how many data will be accessed from the SDRAM in each cache miss.  I maybe could get it from the graph in the CacheTune in the past. But as you have said "The information given by the tool is not always reliable and support for it was dropped long ago." 

    So is there some functionality could help me to find out  when and where the cache miss occurs and how many data will be accessed from the SDRAM in each cache miss.?

    Thanks.

    Lijie

  • 0 in reply to lijie Wang
    TI__Guru**** 483141 points

    Lijie,

    The CCSv3 profiler is your best bet. Note that CCSv3 itself is no longer a supported tool. There are some new tools we have that can help analyze data collected with hw trace, including cache information, but it is not supported on v3. Sorry.

    ki

  • 0 in reply to Ki
    Prodigy 230 points

    Ki, 

    Thank you for reminding me "CCSv3 itself is no longer a supported tool."  I have got it.  

    And I have already bought  the CCS4.2 IDE and Wintech XDC560v2 Emulator which can support the hardware trace functionality. 

    But I have two questions about it:

    1. Could I find out  when and where the cache miss occurs and how many data will be accessed from the SDRAM in each cache miss through the hardware trace?

    2. Is the hardware trace functionality  supported by the whole TI DSPs (such as TMs320DM642)?  Or  only some special DSPs?

    Thanks.

    Lijie