This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linking problem



dear Sir/Mrs. 

We are deveoping a big application on TMDSEVM6678LE using the evalutaion board.. We get the folowing error message: Overlapping in memory area between the   MSMCSRAM    and the SHRAM. In addition, the same problem exist for DDR3 and COR0_DDR3. How to overcome this problem.

Best regards,

Yehuda

  L2SRAM                00800000   00080000  00080000  00000000  RW X

  SHRAM                 0c000000   00010000  0000b704  000048fc  RWIX

  MSMCSRAM              0c000000   00400000  00000000  00400000  RW X

  MSMCSRAM              0c100000   00200000  00000000  00200000  RWIX

  CORE0_L2_SRAM         10800000   00080000  00000000  00080000  RWIX

  CORE0_L1P_SRAM        10e00000   00008000  00000000  00008000  RWIX

  CORE0_L1D_SRAM        10f00000   00008000  00000000  00008000  RWIX

  CORE1_L2_SRAM         11800000   00080000  00000000  00080000  RWIX

  CORE1_L1P_SRAM        11e00000   00008000  00000000  00008000  RWIX

  CORE1_L1D_SRAM        11f00000   00008000  00000000  00008000  RWIX

  CORE2_L2_SRAM         12800000   00080000  00000000  00080000  RWIX

  CORE2_L1P_SRAM        12e00000   00008000  00000000  00008000  RWIX

  CORE2_L1D_SRAM        12f00000   00008000  00000000  00008000  RWIX

  CORE3_L2_SRAM         13800000   00080000  00000000  00080000  RWIX

  CORE3_L1P_SRAM        13e00000   00008000  00000000  00008000  RWIX

  CORE3_L1D_SRAM        13f00000   00008000  00000000  00008000  RWIX

  CORE4_L2_SRAM         14800000   00080000  00000000  00080000  RWIX

  CORE4_L1P_SRAM        14e00000   00008000  00000000  00008000  RWIX

  CORE4_L1D_SRAM        14f00000   00008000  00000000  00008000  RWIX

  CORE5_L2_SRAM         15800000   00080000  00000000  00080000  RWIX

  CORE5_L1P_SRAM        15e00000   00008000  00000000  00008000  RWIX

  CORE5_L1D_SRAM        15f00000   00008000  00000000  00008000  RWIX

  CORE6_L2_SRAM         16800000   00080000  00000000  00080000  RWIX

  CORE6_L1P_SRAM        16e00000   00008000  00000000  00008000  RWIX

  CORE6_L1D_SRAM        16f00000   00008000  00000000  00008000  RWIX

  CORE7_L2_SRAM         17800000   00080000  00000000  00080000  RWIX

  CORE7_L1P_SRAM        17e00000   00008000  00000000  00008000  RWIX

  CORE7_L1D_SRAM        17f00000   00008000  00000000  00008000  RWIX

  EMIF16_CS2            70000000   04000000  00000000  04000000  RWIX

  EMIF16_CS3            74000000   04000000  00000000  04000000  RWIX

  EMIF16_CS4            78000000   04000000  00000000  04000000  RWIX

  EMIF16_CS5            7c000000   04000000  00000000  04000000  RWIX

  CORE0_DDR3            80000000   10000000  00000000  10000000  RWIX

  DDR3                  80000000   20000000  00000000  20000000  RWIX

  CORE1_DDR3            90000000   10000000  00000000  10000000  RWIX

  CORE2_DDR3            a0000000   10000000  00000000  10000000  RWIX

  CORE3_DDR3            b0000000   10000000  00000000  10000000  RWIX

  CORE4_DDR3            c0000000   10000000  00000000  10000000  RWIX

  CORE5_DDR3            d0000000   10000000  00000000  10000000  RWIX

  CORE6_DDR3            e0000000   10000000  00000000  10000000  RWIX

  CORE7_DDR3            f0000000   10000000  00000000  10000000  RWIX

  L2SRAM                00800000   00080000  00080000  00000000  RW X

  SHRAM                 0c000000   00010000  0000b704  000048fc  RWIX

   CORE0_L2_SRAM         10800000   00080000  00000000  00080000  RWIX

  CORE0_L1P_SRAM        10e00000   00008000  00000000  00008000  RWIX

  CORE0_L1D_SRAM        10f00000   00008000  00000000  00008000  RWIX

  CORE1_L2_SRAM         11800000   00080000  00000000  00080000  RWIX

  CORE1_L1P_SRAM        11e00000   00008000  00000000  00008000  RWIX

  CORE1_L1D_SRAM        11f00000   00008000  00000000  00008000  RWIX

  CORE2_L2_SRAM         12800000   00080000  00000000  00080000  RWIX

  CORE2_L1P_SRAM        12e00000   00008000  00000000  00008000  RWIX

  CORE2_L1D_SRAM        12f00000   00008000  00000000  00008000  RWIX

  CORE3_L2_SRAM         13800000   00080000  00000000  00080000  RWIX

  CORE3_L1P_SRAM        13e00000   00008000  00000000  00008000  RWIX

  CORE3_L1D_SRAM        13f00000   00008000  00000000  00008000  RWIX

  CORE4_L2_SRAM         14800000   00080000  00000000  00080000  RWIX

  CORE4_L1P_SRAM        14e00000   00008000  00000000  00008000  RWIX

  CORE4_L1D_SRAM        14f00000   00008000  00000000  00008000  RWIX

  CORE5_L2_SRAM         15800000   00080000  00000000  00080000  RWIX

  CORE5_L1P_SRAM        15e00000   00008000  00000000  00008000  RWIX

  CORE5_L1D_SRAM        15f00000   00008000  00000000  00008000  RWIX

  CORE6_L2_SRAM         16800000   00080000  00000000  00080000  RWIX

  CORE6_L1P_SRAM        16e00000   00008000  00000000  00008000  RWIX

  CORE6_L1D_SRAM        16f00000   00008000  00000000  00008000  RWIX

  CORE7_L2_SRAM         17800000   00080000  00000000  00080000  RWIX

  CORE7_L1P_SRAM        17e00000   00008000  00000000  00008000  RWIX

  CORE7_L1D_SRAM        17f00000   00008000  00000000  00008000  RWIX

  EMIF16_CS2            70000000   04000000  00000000  04000000  RWIX

  EMIF16_CS3            74000000   04000000  00000000  04000000  RWIX

  EMIF16_CS4            78000000   04000000  00000000  04000000  RWIX

  EMIF16_CS5            7c000000   04000000  00000000  04000000  RWIX

  CORE0_DDR3            80000000   10000000  00000000  10000000  RWIX

  DDR3                  80000000   20000000  00000000  20000000  RWIX

  CORE1_DDR3            90000000   10000000  00000000  10000000  RWIX

  CORE2_DDR3            a0000000   10000000  00000000  10000000  RWIX

  CORE3_DDR3            b0000000   10000000  00000000  10000000  RWIX

  CORE4_DDR3            c0000000   10000000  00000000  10000000  RWIX

  CORE5_DDR3            d0000000   10000000  00000000  10000000  RWIX

  CORE6_DDR3            e0000000   10000000  00000000  10000000  RWIX

  CORE7_DDR3            f0000000   10000000  00000000  10000000  RWIX

  • As you can see, the memory window for SHRAM and MSMCRAM overlap. Hence the error.
    Looks like your appliation needs about 0x10000 of SHMEM.

    This is placed at base of MSM RAM memory(total size of 4M).

    So maybe you can split the MSM RAM region as follows:

    Name                   Start              Size
    SHRAM               0c000000       00010000
    MSMCSRAM      0c010000       003f0000
    (any name is ok)

    If possible, please share your linker command file.

  • Dear Varada, 

    Thank you for your answer. We use the c6678_unified.cmd file supplied by Texas Instruments.

    best regards,

    Yehuda

  • The only c6678_unified.cmd link command file I can find from TI is here.  And it is very different from the linker command file you are using.  Moreover, such linker command files are provided only as a starting point.  Most users need to change these files a bit to match their actual system.

    Thanks and regards,

    -George

  • Dr.Singer,

     Hopefully you resolved the linker error.

    Based on the application you are trying to build, there can be other  example linker command files and also example projects, that you can reference.

    So can you describe  what you are trying to build? Are you planning to build an application that is run on multiple cores?

    Single program for multiple cores ? Or a different program on each core.

    And do you plan to use BIOS, ....etc 


     

  • Dear Varada

    Thank you for contacting me. I did not resolve the linking problem. THere is a bug also in the original file. If I change the original file, the linker does not use it. THe lnk.cmd file is generated from other templates of the CCS5.

    We develop a demo for TI to show new paradigm that can use efficiently the multi-core platform.  We use the BIOS6.

    Enclosed please findtwo files aith information that may interrest you.

    Best regards,

    Yehuda

    3187.Energy Saving Version 0.2.pdf7635.PS paradigm _accelrtn full Wk-ld_ 20.9.2011 Version 0.0.pdf

  • If you are using BIOS6, it will automatically create a linker command file for you based on the platform selection. It looks like you have also added c6678_unified.cmd to the project and the MEMORY regions in the two files are conflicting. The c6678_unified.cmd is provided for use when working with non-BIOS projects. If you are working with a BIOS project, removing the c6678_unified.cmd file should help resolve the linker errors.

  • Thanks for sharing the information about your project

     As the previous post mentions, if you are using BIOS6, do not include a linker command file. Instead all the changes can be made in the platform file.

     One thing to note is if you have programs running on multiple cores of the device, you may want to partition the shared memory for each core, so that they do not interfere by using the same memory space at program load and run time.

     

    For example : MSM RAM of 4MB is a shared memory resource. So is DDR3 (EVM has 512MB only).

     

    Below is a post you can refer to for similar scenario.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/144510/522021.aspx#522021

     

    you can also create your own custom RTSC platform file.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/163907.aspx

     

    This is a slightly old demo, as it is for CCSv4, nevertheless helpful

    http://rtsc.eclipse.org/docs-tip/Demo_of_the_RTSC_Platform_Wizard_in_CCSv4

     

  • Dear Varada

    Thanks for your Email. There is an improvement, but still the build process fails. 

    BTW, As a TI employee, I would like to open a conversation and send you the project.

    Best ergards,

    Yehuda

    Error Message:

    Description Resource Path Location Type
    errors encountered during linking; "RISC_Demo_EVM66788L_Version_0.0.out" not built RISC_Demo_EVM66788L_Version_0.0 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10234.html">[?]</a> unresolved symbols remain RISC_Demo_EVM66788L_Version_0.0 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd run placement fails for object "GROUP_1", size 0x2b8 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 122 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd run placement fails for object ".stack", size 0x1000 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 121 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd run placement fails for object ".fardata", size 0x3432 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 133 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd run placement fails for object ".far", size 0x653fa (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 136 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd run placement fails for object ".cio", size 0x123 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 138 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd placement fails for object ".vecs", size 0x5ff (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 140 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd placement fails for object ".text", size 0xdd4de (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 119 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd placement fails for object ".switch", size 0x97a (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 134 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd placement fails for object ".init_array", size 0x154 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 130 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd placement fails for object ".const", size 0x1f1d4 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 131 C/C++ Problem
    <a href="file:/C:/ti/ccsv5/tools/compiler/dmed/HTML/10099.html">#10099-D</a> ./configPkg/linker.cmd placement fails for object ".cinit", size 0x8f3 (page 0). Available ranges: L2SRAM size: 0x80000 unused: 0x0 max hole: 0x0 RISC_Demo_EVM66788L_Version_0.0 line 128 C/C++ Problem

  • Dr.Singer,

     

    Ohh. You still have link issues. As seen by the logs, sections like ‘stack’, ‘.fardata’, ‘.text’ etc  are all being placed in L2SRAM and the size of L2SRAM is limited. You can instead place these sections in MSM RAM. Are you using a linker command file .cmd file in your project ? Can you please attach it in the forum.

    Since you want to use BIOS6, are you creating a RTSC project? Have you selected the RTSC platform for your project ? When you create a RTSC project, the CCS wizard will ask you to pick a platform file. In this wizard, if you choose c6678 as your device, then there is an option in the drop down menu to pick ‘ti.platforms.evm667l’.  I am attaching snapshots for reference. 

     

    Also we at TI will be interested to know about our project. I will let you know the contact of team that is involved in benchmarking.

     

    Hope this helps

  • Attaching the snapshots.

  • Dear Varada

    Thanks for your response. I get the same screen snap-shot. 

  • If you are using the RTSC platform and need to modify the allocation to move code or data from L2SRAM to MSMCSRAM as suggested by Varada, you need to edit the RTSC platform file. To do this, go into the CCS Debug perspective, menu Tools->RTSC Tools->Platform->Edit/View. Make sure the Repository points to the xdctools\packages directory within your CCS installation. For package name, select your package: ti.platforms.evm6678. Click Next.

    That should bring up the Device Page where you can edit allocations. For instance you can change Code Memory to go into MSMCSRAM instead of L2SRAM. In your case moving the code section alone may be enough, but if it is not you may have to alter some of the other allocations as well, but this would be the procedure to do it.