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optimization effects the timer

serdar
Intellectual 390 points

Hi,

I use L138, CGT 7.3.1 and CCS5.1. I have a code to read ADC without BIOS. I used timer2 and compare registers to provide timing for 8 channels of ADC. It works well with -o0 or -o1 compiler optimization. But if I set optimization to -o2 or -o3, timer2 doesn't work. Timer2 isr runs 2 or 3 times (random times) instead of 8 times. I check the timer registers by memory browser. It seems ok, all the registers have correct value.

How could optimization level effect the timer setup or isr?

Thanks in advance

Serdar

  • 0
    TI__Guru* 84110 points

    Serdar,

    Because this is a compiler question and not a C67x device question, we will move this thread to the compiler forum for the best advice.

    The first thing I would look at is whether a memory mapped register is being accessed without using the "volatile" keyword. The optimizer may decide that an access does not need to be repeated each time in a loop.

    The next technique for finding the problem is to selectively apply the optimization on a file-by-file basis. In CCS, you can select to change a compiler option such as optimization for each source file individually. There may be a way to do this with #pragma's on a function basis, but I am not positive about that. This way, you can narrow down which file's optimization is causing the problem.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 390 points

    Hi,

    Randy is right "volatile" keyword solved the problem. I only write to the register, no read so compiler eliminates it.

    Thanks

    // IO switch macro
volatile uint32_t *gpioPtr = (uint32_t *)0x1e26064;
#define CONVST_LOW		*gpioPtr = 0;
#define CONVST_HIGH		*gpioPtr = 0x400000;