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A big difference between TMS320C6x C/C++ Codegen PC v7.3.1 and v5.1.0?

Hi,

I just got CCS 5.2 work on my PC. I run the optimization tutorial (tutor_d.c, lesson_c.c, lesson1_c.c, lesson2_c.c and lesson3_c.c from CCS 3.1) on CCS 5.2. I find that the v7.3.1 compiling results are different from v.5.3.1 of CCS 3.1.

v7.3.1:

;*********** ;* TMS320C6x C/C++ Codegen PC v7.3.1 * ;* Date/Time created: Thu Jun 14 11:01:16 2012                                *

;***********  .compiler_opts --abi=coffabi --c64p_l1d_workaround=default --endian=little --hll_source=on --long_precision_bits=40 --mem_model:code=near --mem_model:const=data --mem_model:data=far_aggregates --object_format=coff --silicon_version=6200 --symdebug:dwarf

;******* ;* GLOBAL FILE PARAMETERS                                                     * 

;*   Architecture      : TMS320C620x                                          * ;*   Optimization      : Enabled at level 3                                   * ;*   Optimizing for    : Speed                                                * ;*                       Based on options: -o3, no -ms                        * ;*   Endian            : Little                                               * ;*   Interrupt Thrshld : Disabled                                             * ;*   Data Access Model : Far Aggregate Data                                   * ;*   Pipelining        : Enabled                                              * ;*   Speculate Loads   : Enabled with threshold = 0                           * ;*   Memory Aliases    : Presume are aliases (pessimistic)                    * ;*   Debug Info        : DWARF Debug                                          * ;*                                                                            * ;*******

v5.3.1:

;* TMS320C6x C/C++ Codegen                                          PC v5.1.0 * ;* Date/Time created: Wed Jun 13 03:25:28 2012                                *

;********  .compiler_opts --endian=little --mem_model:code=near --mem_model:data=far_aggregates --quiet --silicon_version=6210

;********** ;* GLOBAL FILE PARAMETERS                                                     * ;*                                                                            *

;*   Architecture      : TMS320C621x                                          * ;*   Optimization      : Enabled at level 3                                   * ;*   Optimizing for    : Speed                                                * ;*                       Based on options: -o3, no -ms                        * ;*   Endian            : Little                                               * ;*   Interrupt Thrshld : Disabled                                             * ;*   Data Access Model : Far Aggregate Data                                   * ;*   Pipelining        : Enabled                                              * ;*   Speculate Loads   : Disabled                                             * ;*   Memory Aliases    : Presume are aliases (pessimistic)                    *

;*   Debug Info        : DWARF Debug                                          *

BTW, I cannot change the architecture in CCS 5.2 from TMS320C620x to TMS320C621x as that of CCS3.1. I do not find any option can change that.

The more important thing is the software pipeline result differences:

v7.3.1:

;*   SOFTWARE PIPELINE INFORMATION ;* ;*      Loop source line                 : 35 ;*      Loop opening brace source line   : 36 ;*      Loop closing brace source line   : 40 ;*      Loop Unroll Multiple             : 2x ;*      Known Minimum Trip Count         : 5                    ;*      Known Max Trip Count Factor      : 1 ;*      Loop Carried Dependency Bound(^) : 0 ;*      Unpartitioned Resource Bound     : 3 ;*      Partitioned Resource Bound(*)    : 3 ;*      Resource Partition: ;*                                A-side   B-side ;*      .L units                     0        0     ;*      .S units                     2        1     ;*      .D units                     3*       3*    ;*      .M units                     2        2     ;*      .X cross paths               1        1     ;*      .T address paths             3*       3*    ;*      Long read paths              1        1     ;*      Long write paths             0        0     ;*      Logical  ops (.LS)           1        1     (.L or .S unit) ;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit) ;*      Bound(.L .S .LS)             2        1     ;*      Bound(.L .S .D .LS .LSD)     2        2     ;* ;*      Searching for software pipeline schedule at ... ;*         ii = 3  Schedule found with 5 iterations in parallel ;*      Done ;* ;*      Epilog not removed ;*      Collapsed epilog stages       : 0 ;* ;*      Prolog not entirely removed ;*      Collapsed prolog stages       : 3 ;* ;*      Minimum required memory pad   : 0 bytes ;* ;*      For further improvement on this loop, try option -mh16 ;* ;*      Minimum safe trip count       : 4 (after unrolling)

v5.3.1:

;*   SOFTWARE PIPELINE INFORMATION ;* ;*      Loop source line                 : 35 ;*      Loop opening brace source line   : 36 ;*      Loop closing brace source line   : 40 ;*      Loop Unroll Multiple             : 2x ;*      Known Minimum Trip Count         : 5                    ;*      Known Max Trip Count Factor      : 1 ;*      Loop Carried Dependency Bound(^) : 1 ;*      Unpartitioned Resource Bound     : 2 ;*      Partitioned Resource Bound(*)    : 2 ;*      Resource Partition: ;*                                A-side   B-side ;*      .L units                     0        0     ;*      .S units                     2*       1     ;*      .D units                     2*       2*    ;*      .M units                     2*       2*    ;*      .X cross paths               1        1     ;*      .T address paths             2*       2*    ;*      Long read paths              1        1     ;*      Long write paths             0        0     ;*      Logical  ops (.LS)           1        1     (.L or .S unit) ;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit) ;*      Bound(.L .S .LS)             2*       1     ;*      Bound(.L .S .D .LS .LSD)     2*       2*    ;* ;*      Searching for software pipeline schedule at ... ;*         ii = 2  Schedule found with 6 iterations in parallel ;* ;*      Register Usage Table: ;*          +---------------------------------+ ;*          |AAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBB| ;*          |0000000000111111|0000000000111111| ;*          |0123456789012345|0123456789012345| ;*          |----------------+----------------| ;*       0: | * *******      |*** ******      | ;*       1: | * *******      |*** ******      | ;*          +---------------------------------+ ;* ;*      Done ;* ;*      Epilog not entirely removed ;*      Collapsed epilog stages     : 2 ;* ;*      Prolog not entirely removed ;*      Collapsed prolog stages     : 3 ;* ;*      Minimum required memory pad : 0 bytes ;* ;*      For further improvement on this loop, try option -mh20 ;* ;*      Minimum safe trip count     : 3 (after unrolling)

........................

It seems v7.3.1 result is not as good as that of v5.3.1. On CCS5.2, I do not find where to change to -mh16 as CCS5.2 recommands. Is my result true? Or, I miss something? Thanks in advance.