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Difference in measured cycle count on CCSv3.1 and CCSv4/CCSv5

Rahul Prabhu
Guru** 116170 points

Hi CCS champs,

We have strange issue reported on C5509 cycle count measurmeents in CCS while running some performance benchmarks. The benchmarking was run on CCS v3.1 and CCS v4/v5. Here are the details:

In CCS v4.x/5.x cycle count measured for duration of for which ADCBUSY signal is high was as mentioned below:

  1st iteration: 2145 cycles (14.9uS, because System Clock is set as 144MHz)

  2nd iteration: 2344 cycles (16.3uS, because System Clock is set as 144MHz)

  3rditeration : 2338 cycles (16.2uS, because System Clock is set as 144MHz)

 

But if CCS v3.1 cycle count for duration for which the signal ADCBUSY signal is high was as mentioned below:

  1st iteration: 6839 cycles (47.1uS, because System Clock is set as 144MHz)

  2nd iteration: 6851 cycles (47.2uS, because System Clock is set as 144MHz)

  3rd iteration: 6833 cycles (47.1uS, because System Clock is set as 144MHz)

Can someone explain the difference in the cycle count measurement between CCSv3.1 and CCSv4/v5.  The signal when measured on the oscilloscope proved that the measurements on CCSv3.1 were indeed accurate.The measurements were made on the device and not on the simulator.

Regards,

Rahul

  • TI__Guru**** 463901 points

    Hi Rahul,

    How are you doing your benchmarking with CCS? Are you using the profile clock? If so, make sure the event being counted by the clock is the same between CCSv3 and v4/5. Most devices just support counting CPU cycles but some do support counting other events (not sure what events are supported on a C5509).

    ki