Target Configuration file not highlighted, example program will not load

Hi Pat,

Pat Harris said:

I normally see the selected config file highlighted, but not in this case.

If the file is in your project, then it should be fine. If it is part of the 'User Defined' list in the 'Target Configurations' view, then you need to right-click on it and select 'Set as Default'.

Pat Harris said:

C28xx_0: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

Assuming the correct target configuration file is being used when starting a debug session, do you recall what address it was trying to load to when this error occurred? I believe in the load program progress bar, it will tell you the section and address being loaded. Also are you using a gel file for your target configuration? The default is 'f28m35h52c1_c28.gel'.

Thanks

ki

Hi Ki,

Thanks for your response. I am using the example as given. My Target config file is a .ccxml. There is no .gel file listed in the Project Explorer file list. Where do I get that?

My latest attempt is with adc_soc_c28 example and I get the same results.

Thanks,

Pat

Pat,

The example as given does not come with a ccxml file. At least the version of controlSUITE I have didn't come with one. So I assume you created one for your device. The gel file would not show up in the Project Explorer list, but under the 'Advanced' tab of the Target Configuration editor (under 'initialization script'):

See slide 78 of: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_ccstudio/workshops/CCSv5/C2000/CCSv5-Workshop%28C2000%29_2.pdf

You can also see what gel file was used for an existing debug session with the 'GEL Files' view:

See slide 82 of: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_ccstudio/workshops/CCSv5/C2000/CCSv5-Workshop%28C2000%29_2.pdf

Thanks

ki

I running V5.2. I don't have any information displayed on the right side of the target configuration display as shown in the slide??

Did you make sure your are in the 'Advanced' tab (see the three tabs at the bottom)?

Yes I am. I only have the "All Connections" section. Nothing else.

Here is the error message I get when attempting to run the adc_soc_c28 example:

C:/TI5/TI5_1/ccsv5/tools/compiler/c2000_6.0.3/lib/rts2800_fpu32.lib<boot.ob j>" specifies ISA revision "C28FPU32", which is not compatible with ISA revision "C2800" specified in a previous file or on the command line

Well, I'm not sure just what fixed the problem, but Iwent to the General properties, changed the variant to F28M35H52C1, changed the linker and runtime , then changed them back, with the variant still F28M35H52C1 and it compiled. Hmmm.... But, I still cannot debug, getting the same error as above.

I was able to access GEL Files and the Script f28m35h52c1_c28.gel is listed.with the status of success. Here's the text:

/********************************************************************/

/* f28m35h52c1_c28.gel                                              */

/* Version 4.00.0                                                   */

/*                                                                  */

/* This GEL file is to be used with the F28M35H52C1 Device.         */

/* Changes may be required to support specific hardware designs.    */

/*                                                                  */

/* Code Composer Studio supports six reserved GEL functions that    */

/* automatically get executed if they are defined. They are:        */

/*                                                                  */

/* StartUp()              - Executed whenever CCS is invoked        */

/* OnReset()              - Executed after Debug->Reset CPU         */

/* OnRestart()            - Executed after Debug->Restart           */

/* OnPreFileLoaded()      - Executed before File->Load Program      */

/* OnFileLoaded()         - Executed after File->Load Program       */

/* OnTargetConnect()      - Executed after Debug->Connect           */

/*                                                                  */

/********************************************************************/

StartUp()

{

}

OnReset(int nErrorCode)

{

    if (GEL_IsInRealtimeMode())   /* If in real-time-mode */

    {

    }

    else    /* Put device in C28x mode */

    {

         C28x_Mode();

    }

    Unlock_CSM();

    Unlock_ECSL();

    ReadFlashEXE();

    C28x_Disable_Flash_ECC();

}

OnRestart(int nErrorCode)

{

/* CCS will call OnRestart() when you do a Debug->Restart and   */

/* after you load a new file.  Between running interrupt based  */

/* programs, this function will clear interrupts and help keep  */

/* the processor from going off into invalid memory.            */

     if (GEL_IsInRealtimeMode())   /* If in real-time-mode */

    {

    }

    else    /* Put device in C28x mode */

    {

         C28x_Mode();

    }

     IER = 0;

     IFR = 0;

}

OnPreFileLoaded()

{

     GEL_Reset();

    // C28x_Ram_Init();             /* WARNING: If C28x_Ram_Init() is uncommented,            */

                                    /* any other code in RAM will be re-initialized to 0x0000 */

                                    /* on any file load                                       */

}

OnFileLoaded(int nErrorCode, int bSymbolsOnly)

{

     if (!bSymbolsOnly) {

     }

}

OnTargetConnect()

{

    if (GEL_IsInRealtimeMode())   /* If in real-time-mode */

    {

    }

    else    /* Put device in C28x mode */

    {

         C28x_Mode();

    }

    F28M35H52C1_Memory_Map();        /* Initialize the CCS memory map */

    C28x_Ram_Init();                 /* WARNING: If C28x_Ram_Init() is uncommented,  */

                                     /* code in RAM will be re-initialized to 0x0000 */

                                     /* on a target disconnect and reconnect.        */

    C28x_Disable_Flash_ECC();

/* Check to see if CCS has been started-up with the DSP already */

/* running in real-time mode.  The user can add whatever        */

/* custom initialization stuff they want to each case.          */

    if (GEL_IsInRealtimeMode())     /* Do real-time mode target initialization */

    {

    }

    else                            /* Do stop-mode target initialization */

    {

        GEL_Reset();                /* Reset DSP */

    }

}

/********************************************************************/

/* These functions are launched by the GEL_Toolbar button plugin    */

/********************************************************************/

GEL_Toolbar1()

{

    Run_Realtime_with_Reset();

}

GEL_Toolbar2()

{

    Run_Realtime_with_Restart();

}

GEL_Toolbar3()

{

    Full_Halt();

}

GEL_Toolbar4()

{

    Full_Halt_with_Reset();

}

GEL_Toolbar5()

{

    Full_Halt_with_Reset();

    GEL_Restart();

}

/********************************************************************/

/* These functions are useful to engage/disengage realtime          */

/* emulation mode during debug.  They save the user from having to  */

/* manually perform these steps in CCS.                             */

/********************************************************************/

menuitem "Realtime Emulation Control";

hotmenu Run_Realtime_with_Reset()

{

    GEL_Reset();                /* Reset the DSP */

    ST1 = ST1 & 0xFFFD;         /* clear DBGM bit in ST1 */

    GEL_EnableRealtime();       /* Enable Realtime mode */

    GEL_Run();                  /* Run the DSP */

}

hotmenu Run_Realtime_with_Restart()

{

    GEL_Restart();              /* Reset the DSP */

    ST1 = ST1 & 0xFFFD;         /* clear DBGM bit in ST1 */

    GEL_EnableRealtime();       /* Enable Realtime mode */

    GEL_Run();                  /* Run the DSP */

}

hotmenu Full_Halt()

{

    GEL_DisableRealtime();      /* Disable Realtime mode */

    GEL_Halt();                 /* Halt the DSP */

}

hotmenu Full_Halt_with_Reset()

{

    GEL_DisableRealtime();      /* Disable Realtime mode */

    GEL_Halt();                 /* Halt the DSP */

    GEL_Reset();                /* Reset the DSP */

}

/*********************************************************************/

/*                         F28M35H52C1 Memory Map                    */

/*                                                                   */

/*   Note: M0M1MAP and VMAP signals tied high on F28M35H52C1 core    */

/*                                                                   */

/*   0x000000 - 0x0003ff   M0 SARAM                 (Prog and Data)  */

/*   0x000400 - 0x0007ff   M1 SARAM                 (Prog and Data)  */

/*   0x000800 - 0x001fff   Peripheral Frame0  (PF0) (Data only)      */

/*   0x004000 - 0x004fff   Peripheral Frame1  (PF1) (Data only)      */

/*   0x005000 - 0x006fff   Peripheral Frame3  (PF3) (Data only)      */

/*   0x007000 - 0x007fff   Peripheral Frame2  (PF2) (Data only)      */

/*   0x008000 - 0x008fff   L0 SARAM                 (Prog and Data)  */

/*   0x009000 - 0x009fff   L1 SARAM                 (Prog and Data)  */

/*   0x00a000 - 0x00afff   L2 SARAM                 (Prog and Data)  */

/*   0x00b000 - 0x00bfff   L3 SARAM                 (Prog and Data)  */

/*   0x00c000 - 0x00cfff   S0 SARAM                 (Prog and Data)  */

/*   0x00d000 - 0x00dfff   S1 SARAM                 (Prog and Data)  */

/*   0x00e000 - 0x00efff   S2 SARAM                 (Prog and Data)  */

/*   0x00f000 - 0x00ffff   S3 SARAM                 (Prog and Data)  */

/*   0x010000 - 0x010fff   S4 SARAM                 (Prog and Data)  */

/*   0x011000 - 0x011ff    S5 SARAM                 (Prog and Data)  */

/*   0x012000 - 0x012fff   S6 SARAM                 (Prog and Data)  */

/*   0x013000 - 0x013fff   S7 SARAM                 (Prog and Data)  */

/*   0x03f800 - 0x03fbff   CtoM MSGRAM              (Data only)      */

/*   0x03fc00 - 0x03ffff   MtoC MSGRAM              (Data only)      */

/*     0x048000 - 0x048fff   L0 RAM - ECC Bits        (Data only)         */

/*   0x049000 - 0x049fff   L1 RAM - ECC Bits        (Data only)         */

/*   0x04a000 - 0x04afff   L2 RAM - PARITY Bits     (Data only)      */

/*   0x04b000 - 0x04bfff   L3 RAM - PARITY Bits     (Data only)      */

/*   0x04c000 - 0x04cfff   S0 RAM - PARITY Bits     (Data only)      */

/*   0x04d000 - 0x04dfff   S1 RAM - PARITY Bits     (Data only)      */

/*   0x04e000 - 0x04efff   S2 RAM - PARITY Bits     (Data only)      */

/*   0x04f000 - 0x04ffff   S3 RAM - PARITY Bits     (Data only)      */

/*   0x050000 - 0x050fff   S4 RAM - PARITY Bits     (Data only)      */

/*   0x051000 - 0x051fff   S5 RAM - PARITY Bits     (Data only)      */

/*   0x052000 - 0x052fff   S6 RAM - PARITY Bits     (Data only)      */

/*   0x052000 - 0x053fff   S7 RAM - PARITY Bits     (Data only)      */

/*     0x07f000 - 0x07f3ff   M0 RAM - ECC Bits        (Data only)         */

/*   0x07f400 - 0x07f7ff   M1 RAM - ECC Bits        (Data only)         */

/*   0x07f800 - 0x07fbff   C28toM3 MSGRAM - PARITY Bits (Data only)  */

/*   0x07fc00 - 0x07ffff   M3toC28 MSGRAM - PARITY Bits (Data only)  */

/*   0x100000 - 0x10ffff   FLASH BANK 2             (Prog and Data)  */

/*     0x200000 - 0x207fff   FLASH BANK 2 ECC Bits    (Data only)         */

/*     0x240000 - 0x2403ff   OTP BANK 2                (Data only)         */

/*   0x280000 - 0x28007f   OTP BANK 2 ECC Bits        (Data only)         */

/*   0x3e0000 - 0x3effff   BIST ROM                 (Prog and Data)  */

/*   0x3f8000 - 0x3fffff   BOOT ROM                 (Prog and Data)  */

/*********************************************************************/

menuitem "Initialize Control Subsystem 28x Memory Map";

hotmenu F28M35H52C1_Memory_Map()

{

    GEL_MapReset();

    GEL_MapOn();

    /* Program memory maps */

    GEL_MapAdd(0x0,0,0x400,1,1);                /* M0 SARAM */

    GEL_MapAdd(0x400,0,0x400,1,1);              /* M1 SARAM */

    GEL_MapAdd(0xd00,0,0x100,1,1);                /* PIEVECT(DSPBIOS) */

    GEL_MapAdd(0x8000,0,0x1000,1,1);            /* L0 SARAM */

    GEL_MapAdd(0x9000,0,0x1000,1,1);            /* L1 SARAM */

    GEL_MapAdd(0xa000,0,0x1000,1,1);            /* L2 SARAM */

    GEL_MapAdd(0xb000,0,0x1000,1,1);            /* L3 SARAM */

    GEL_MapAdd(0xc000,0,0x1000,1,1);            /* S0 SARAM */

    GEL_MapAdd(0xd000,0,0x1000,1,1);            /* S1 SARAM */

    GEL_MapAdd(0xe000,0,0x1000,1,1);            /* S2 SARAM */

    GEL_MapAdd(0xf000,0,0x1000,1,1);            /* S3 SARAM */

    GEL_MapAdd(0x10000,0,0x1000,1,1);           /* S4 SARAM */

    GEL_MapAdd(0x11000,0,0x1000,1,1);           /* S5 SARAM */

    GEL_MapAdd(0x12000,0,0x1000,1,1);           /* S6 SARAM */

    GEL_MapAdd(0x13000,0,0x1000,1,1);           /* S7 SARAM */

    GEL_MapAdd(0x100000,0,0x40000,1,0);         /* FLASH BANK 2 */

    GEL_MapAdd(0x3f8000,0,0x8000,1,0);          /* BOOT ROM */

    /* Data memory maps */

    GEL_MapAdd(0x0,1,0x400,1,1);                /* M0 SARAM */

    GEL_MapAdd(0x400,1,0x400,1,1);              /* M1 SARAM */

    GEL_MapAdd(0x800,1,0x1800,1,1);             /* PF0 */

    GEL_MapAdd(0x4000,1,0x1000,1,1);            /* PF1 */

    GEL_MapAdd(0x5000,1,0x2000,1,1);            /* PF3 */

    GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */

    GEL_MapAdd(0x8000,1,0x1000,1,1);            /* L0 SARAM */

    GEL_MapAdd(0x9000,1,0x1000,1,1);            /* L1 SARAM */

    GEL_MapAdd(0xa000,1,0x1000,1,1);            /* L2 SARAM */

    GEL_MapAdd(0xb000,1,0x1000,1,1);            /* L3 SARAM */

    GEL_MapAdd(0xc000,1,0x1000,1,1);            /* S0 SARAM */

    GEL_MapAdd(0xd000,1,0x1000,1,1);            /* S1 SARAM */

    GEL_MapAdd(0xe000,1,0x1000,1,1);            /* S2 SARAM */

    GEL_MapAdd(0xf000,1,0x1000,1,1);            /* S3 SARAM */

    GEL_MapAdd(0x10000,1,0x1000,1,1);           /* S4 SARAM */

    GEL_MapAdd(0x11000,1,0x1000,1,1);           /* S5 SARAM */

    GEL_MapAdd(0x12000,1,0x1000,1,1);           /* S6 SARAM */

    GEL_MapAdd(0x13000,1,0x1000,1,1);           /* S7 SARAM */

    GEL_MapAdd(0x3f800,1,0x400,1,1);            /* CtoM MSGRAM */

    GEL_MapAdd(0x3fc00,1,0x400,1,1);            /* MtoC MSGRAM */

    GEL_MapAdd(0x48000,1,0x1000,1,0);            /* L0 RAM - ECC Bits */

    GEL_MapAdd(0x49000,1,0x1000,1,0);            /* L1 RAM - ECC Bits */

    GEL_MapAdd(0x4a000,1,0x1000,1,0);              /* L2 RAM - PARITY Bits */

    GEL_MapAdd(0x4b000,1,0x1000,1,0);           /* L3 RAM - PARITY Bits */

    GEL_MapAdd(0x4c000,1,0x1000,1,0);           /* S0 RAM - PARITY Bits */

    GEL_MapAdd(0x4d000,1,0x1000,1,0);            /* S1 RAM - PARITY Bits */

    GEL_MapAdd(0x4e000,1,0x1000,1,0);           /* S2 RAM - PARITY Bits */

    GEL_MapAdd(0x4f000,1,0x1000,1,0);            /* S3 RAM - PARITY Bits */

    GEL_MapAdd(0x50000,1,0x1000,1,0);           /* S4 RAM - PARITY Bits */

    GEL_MapAdd(0x51000,1,0x1000,1,0);           /* S5 RAM - PARITY Bits */

    GEL_MapAdd(0x52000,1,0x1000,1,0);            /* S6 RAM - PARITY Bits */

    GEL_MapAdd(0x53000,1,0x1000,1,0);            /* S7 RAM - PARITY Bits */

    GEL_MapAdd(0x7f000,1,0x400,1,0);            /* M0 RAM - ECC Bits */

    GEL_MapAdd(0x7f400,1,0x400,1,0);            /* M1 RAM - ECC Bits */

    GEL_MapAdd(0x7f800,1,0x400,1,0);            /* CtoM MSGRAM - PARITY Bits */

    GEL_MapAdd(0x7fc00,1,0x400,1,0);            /* MtoC MSGRAM - PARITY Bits */

    GEL_MapAdd(0x100000,1,0x40000,1,0);         /* FLASH BANK 2 */

    GEL_MapAddStr(0x200000,1,0x8000,"R|AS2",0); /* FLASH BANK 2 ECC Bits */

    GEL_MapAdd(0x240000,1,0x400,1,0);            /* OTP BANK 2 */

    GEL_MapAddStr(0x280000,1,0x80,"R|AS2",0);    /* OTP BANK 2 ECC Bits */

    GEL_MapAdd(0x3f8000,1,0x8000,1,0);          /* BOOT ROM */

    GEL_TextOut("\nMemory Map Initialization Complete\n");

}

/********************************************************************/

/* The ESTOP0 fill functions are useful for debug.  They fill the   */

/* RAM with software breakpoints that will trap runaway code.       */

/********************************************************************/

hotmenu Fill_Control_Subsystem_28x_RAM_with_ESTOP0()

{

    GEL_MemoryFill(0x000000,1,0x000800,0x7625);      /* Fill M0/M1  */

    GEL_MemoryFill(0x008000,1,0x001000,0x7625);      /* Fill L0     */

    GEL_MemoryFill(0x009000,1,0x001000,0x7625);      /* Fill L1     */

    GEL_MemoryFill(0x00a000,1,0x001000,0x7625);      /* Fill L2     */

    GEL_MemoryFill(0x00b000,1,0x001000,0x7625);      /* Fill L3     */

    GEL_MemoryFill(0x00c000,1,0x008000,0x7625);         /* Fill S0-S7  */

}

hotmenu C28x_Ram_Init()

{

    *(unsigned long *)0x4920 |= 0x00000015; /* Initialize M0, M1, CtoM MSG RAM's   */

    *(unsigned long *)0x4922 |= 0x00000055; /* Initialize L0, L1, L2, L3 RAM's */

    while(*(unsigned long *)0x4930 != 0x15);

    while(*(unsigned long *)0x4932 != 0x55);

    GEL_TextOut("\nRAM Initialization Complete\n");

}

hotmenu C28x_Disable_Flash_ECC()

{

    *0x4300 = 0x0; /* Disable Flash ECC */

}

hotmenu C28x_Enable_Flash_ECC()

{

    *0x4300 |= 0xA; /* Enable Flash ECC */

}

/********************************************************************/

menuitem "Code Security Module"

hotmenu Unlock_CSM()

{

    /* Perform dummy reads of the password locations */

    XAR0 = *0x13FFF8;

    XAR0 = *0x13FFFA;

    XAR0 = *0x13FFFC;

    XAR0 = *0x13FFFE;

    /* Write passwords to the KEY registers.  0xFFFFFFFF's are dummy passwords.

       User should replace them with the correct password for their DSP */

    *(unsigned long*)0xAE0 = 0xFFFFFFFF;

    *(unsigned long*)0xAE2 = 0xFFFFFFFF;

    *(unsigned long*)0xAE4 = 0xFFFFFFFF;

    *(unsigned long*)0xAE6 = 0xFFFFFFFF;

}

/********************************************************************/

menuitem "Code Security Module"

hotmenu Unlock_ECSL()

{

    /* Perform dummy reads of the password locations */

    XAR0 = *0x13FFF4;

    XAR0 = *0x13FFF6;

    /* Write passwords to the KEY registers.  0xFFFFFFFF's are dummy passwords.

       User should replace them with the correct password for their DSP */

    *(unsigned long*)0xAF0 = 0xFFFFFFFF;

    *(unsigned long*)0xAF2 = 0xFFFFFFFF;

}

/********************************************************************/

menuitem "Code Security Module"

hotmenu ReadFlashEXE()

{

    /* Perform dummy read of the flash execute only location */

    XAR6 = *0x13FFF2;

}

/********************************************************************/

menuitem "Addressing Modes";

hotmenu C28x_Mode()

{

    ST1 = ST1 & (~0x0100);      /*   AMODE = 0  */

    ST1 = ST1 | 0x0200;         /* OBJMODE = 1  */

}

hotmenu C24x_Mode()

{

    ST1 = ST1 | 0x0100;         /*   AMODE = 1  */

    ST1 = ST1 | 0x0200;         /* OBJMODE = 1  */

}

hotmenu C27x_Mode()

{

    ST1 = ST1 & (~0x0100);      /*   AMODE = 0  */

    ST1 = ST1 & (~0x0200);      /* OBJMODE = 0  */

}

/********************************************************************/

/*** End of file ***/

Pat Harris said:

Yes I am. I only have the "All Connections" section. Nothing else.

You need to make sure you have the right node selected in the tree. the content in the right is context sensitive to the node selected. The gel file would be visible when the actual CPU is selected in the node ('C28xx_0').

Pat Harris said:

Well, I'm not sure just what fixed the problem, but Iwent to the General properties, changed the variant to F28M35H52C1, changed the linker and runtime , then changed them back, with the variant still F28M35H52C1 and it compiled

Yup, having the correct variant specified would help pull in the right stuff.

The GEL file you listed is the default one and according to that, the address range you built for should be supported. I'll see if I can grab a hold of a concerto myself and reproduce this...

Ki,

I get the same error with CCS V4.2. Should the Linker Command File be set to anything?

Thanks,

Pat

I've tried several projects, even blinky. Nothing will load to the C28. I can load the CM3, however.

I'm missing something here concerning the linker / memory map. Any ideas?

Thanks,

Pat

Ki,

Perhaps what's needed here is a hard reset of the core, allowing me to start over trying to program the device. Is there a "CTRL-ALT-DEL" process for this chip?

Pat

The latest error on the V4.2 system is a failure to load program due to "Invalid File Format" on the .out file??

Pat

It may be that a load of the adc_temp_sensor example did occur. I have a continuous terminal output of unintelligible text. Would this be expected if the temp sensor program is running? Would this activity prevent me from another download? If so, how do I kill it so I can load another example? Is there no way to get the terminal to display raw hex data?

Thanks,

Pat

I tried a second module and had no trouble loading the temp_sensor example. I was hesitant for fear that I might propagate this problem, but did not. I must have a flash problem with the module in question - or - is there a way to clear out the flash??

Thanks,

Pat

Pat Harris said:

I must have a flash problem with the module in question - or - is there a way to clear out the flash??

By default, CCS should erase all the flash sectors before programming. You can turn this off or specify which sectors to erase in the flash programmer debugger options. You can check to make sure all the flash sectors are being erased...

Ki

How do you specify the flash sectors to write? The help talks about a On-Chip View but I don't see any tabs for that feature. Where do I find that?

Thanks,

Pat

When you have started a debug session and are in the CCS Debug perspective, go to 'Tools -> On-Chip Flash'.

Apparently yhe GEL select and the On-Chip are only functions accessible in V4.2.5. They don't appear to be included in V5.2. Anyway, I tried to isolate flash sectors in 4.2.5 but when I tried to Erase Flash, it tells me that the target is not connected (it is). Are there any pins on the chip itself that could be used to reset the flash? Should I just send this module back for repair?

Pat

I am able to get the module to work on the CCS 4.2 station. The recurring error on the V5.2 is that

Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

This is acquired when I try to run the adc_temp+sensor_c28 example. Has anyone else had this problem?

Thaanks,

Pat

Making another appeal to TI to help resolve this issue with the adc_temp_sensor_c28 example. Here are both the map file and the linker .cmd file. The linker shows nothing for program memory in page 0, whereas the map does. Is this the problem and how do I solve it?

Thanks to anyone who can help,

Pat

Here is the error:

Cortex_M3_0: GEL Output: Memory Map Initialization Complete

C28xx_0: GEL Output:

Memory Map Initialization Complete

C28xx_0: GEL Output:

RAM Initialization Complete

C28xx_0: Failed Software Reset: (Error -1138 @ 0x0) Device refused to allow debug mode. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.429.0)

C28xx_0: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

C28xx_0: File Loader: Data verification failed at address 0x0013EB78 Please verify target memory and memory map.

Error found during data verification.

Ensure the linker command file matches the memory map.

Map for adc_temp_sensor_c28:

******************************************************************************

             TMS320C2000 Linker PC v6.1.0                     

******************************************************************************

>> Linked Tue Jul 10 11:17:34 2012

OUTPUT FILE NAME:   <adc_temp_sensor_c28.out>

ENTRY POINT SYMBOL: "code_start"  address: 0013fff0

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill

----------------------  --------  ---------  --------  --------  ----  --------

PAGE 0:

  RAML0                 00008000   00001000  00000029  00000fd7  RWIX

  RAML1                 00009000   00001000  00000000  00001000  RWIX

  FLASHG                00120000   00008000  00000000  00008000  RWIX

  FLASHF                00128000   00008000  00000000  00008000  RWIX

  FLASHE                00130000   00008000  00000000  00008000  RWIX

  FLASHD                00138000   00002000  00000029  00001fd7  RWIX

  FLASHC                0013a000   00002000  00000000  00002000  RWIX

  FLASHA                0013e000   00001f80  00000b8e  000013f2  RWIX

  CSM_RSVD              0013ff80   00000070  00000000  00000070  RWIX

  BEGIN                 0013fff0   00000002  00000002  00000000  RWIX

  FLASH_EXE_ONLY_P0     0013fff2   00000002  00000000  00000002  RWIX

  ECSL_PWL_P0           0013fff4   00000004  00000000  00000004  RWIX

  CSM_PWL_P0            0013fff8   00000008  00000000  00000008  RWIX

  FPUTABLES             003fd258   000006a0  00000000  000006a0  RWIX

  IQTABLES              003fd8f8   00000b50  00000000  00000b50  RWIX

  IQTABLES2             003fe448   0000008c  00000000  0000008c  RWIX

  IQTABLES3             003fe4d4   000000aa  00000000  000000aa  RWIX

  BOOTROM               003feda8   00001200  00000000  00001200  RWIX

  PIEMISHNDLR           003fffbe   00000002  00000000  00000002  RWIX

  RESET                 003fffc0   00000002  00000000  00000002  RWIX

  VECTORS               003fffc2   0000003e  00000000  0000003e  RWIX

PAGE 1:

  BOOT_RSVD             00000000   00000050  00000000  00000050  RWIX

  RAMM0                 00000050   000003b0  00000300  000000b0  RWIX

  RAMM1                 00000400   00000400  00000000  00000400  RWIX

  DEV_EMU               00000880   00000180  00000048  00000138  RWIX

  CSM                   00000ae0   00000020  00000016  0000000a  RWIX

  ADC1_RESULT           00000b00   00000020  00000010  00000010  RWIX

  ADC2_RESULT           00000b40   00000020  00000010  00000010  RWIX

  CPU_TIMER0            00000c00   00000008  00000008  00000000  RWIX

  CPU_TIMER1            00000c08   00000008  00000008  00000000  RWIX

  CPU_TIMER2            00000c10   00000008  00000008  00000000  RWIX

  PIE_CTRL              00000ce0   00000020  0000001a  00000006  RWIX

  PIE_VECT              00000d00   00000100  00000100  00000000  RWIX

  PIE_VECT_CP           00000e00   00000100  00000100  00000000  RWIX

  DMA                   00001000   00000200  000000e0  00000120  RWIX

  ASYSCTRLCONFIG        00001700   00000080  00000078  00000008  RWIX

  HWBIST                00001780   00000040  00000000  00000040  RWIX

  FLASH_REGS            00004000   00000300  00000180  00000180  RWIX

  FLASH_ECC             00004300   00000040  00000024  0000001c  RWIX

  M3PLL                 00004400   00000040  00000008  00000038  RWIX

  RAM_REGS              00004900   00000080  0000003e  00000042  RWIX

  RAM_ERR_REGS          00004a00   00000080  0000003e  00000042  RWIX

  CM_MC_IPC             00004e00   00000040  00000040  00000000  RWIX

  MCBSPA                00005000   00000040  00000024  0000001c  RWIX

  EPWM1                 00005100   00000080  00000080  00000000  RWIX

  EPWM2                 00005180   00000080  00000080  00000000  RWIX

  EPWM3                 00005200   00000080  00000080  00000000  RWIX

  EPWM4                 00005280   00000080  00000080  00000000  RWIX

  EPWM5                 00005300   00000080  00000080  00000000  RWIX

  EPWM6                 00005380   00000080  00000080  00000000  RWIX

  EPWM7                 00005400   00000080  00000080  00000000  RWIX

  EPWM8                 00005480   00000080  00000080  00000000  RWIX

  EPWM9                 00005500   00000080  00000080  00000000  RWIX

  ECAP1                 00005a00   00000020  00000020  00000000  RWIX

  ECAP2                 00005a20   00000020  00000020  00000000  RWIX

  ECAP3                 00005a40   00000020  00000020  00000000  RWIX

  ECAP4                 00005a60   00000020  00000020  00000000  RWIX

  ECAP5                 00005a80   00000020  00000020  00000000  RWIX

  ECAP6                 00005aa0   00000020  00000020  00000000  RWIX

  EQEP1                 00005b00   00000040  00000022  0000001e  RWIX

  EQEP2                 00005b40   00000040  00000022  0000001e  RWIX

  EQEP3                 00005b80   00000040  00000022  0000001e  RWIX

  GPIOG1CTRL            00005f80   00000040  00000040  00000000  RWIX

  GPIOG1DAT             00005fc0   00000020  00000020  00000000  RWIX

  GPIOG1TRIP            00005fe0   00000020  00000020  00000000  RWIX

  COMP1                 00006400   00000020  00000007  00000019  RWIX

  COMP2                 00006420   00000020  00000007  00000019  RWIX

  COMP3                 00006440   00000020  00000007  00000019  RWIX

  COMP4                 00006460   00000020  00000007  00000019  RWIX

  COMP5                 00006480   00000020  00000007  00000019  RWIX

  COMP6                 000064a0   00000020  00000007  00000019  RWIX

  GPIOG2CTRL            00006f80   00000040  0000003c  00000004  RWIX

  GPIOG2DAT             00006fc0   00000020  00000020  00000000  RWIX

  SYSTEM                00007010   00000020  0000001d  00000003  RWIX

  SPIA                  00007040   00000010  00000010  00000000  RWIX

  SCIA                  00007050   00000010  00000010  00000000  RWIX

  NMIINTRUPT            00007060   00000010  00000006  0000000a  RWIX

  XINTRUPT              00007070   00000010  00000010  00000000  RWIX

  ADC1                  00007100   00000080  00000050  00000030  RWIX

  ADC2                  00007180   00000080  00000050  00000030  RWIX

  I2CA                  00007900   00000040  00000022  0000001e  RWIX

  RAML2                 0000a000   00001000  00000018  00000fe8  RWIX

  RAML3                 0000b000   00001000  00000000  00001000  RWIX

  CTOMRAM               0003f800   00000380  00000000  00000380  RWIX

  MTOCRAM               0003fc00   00000380  00000000  00000380  RWIX

  FLASHB                0013c000   00002000  00000000  00002000  RWIX

  FLASH_EXE_ONLY        0013fff2   00000002  00000002  00000000  RWIX

  ECSL_PWL              0013fff4   00000004  00000004  00000000  RWIX

  CSM_PWL               0013fff8   00000008  00000008  00000000  RWIX

Linker .cmd file for adc_temp_sensor_c28:

/*

//###########################################################################

// FILE:    F28M35x_Headers_nonBIOS.cmd

// TITLE:   F28M35x Peripheral registers linker command file

// DESCRIPTION:

//          This file is for use in Non-BIOS applications.

//          Linker command file to place the peripheral structures

//          used within the F28M35x headerfiles into the correct memory

//          mapped locations.

//          This version of the file includes the PieVectorTable structure.

//          For BIOS applications, please use the F28M35x_Headers_BIOS.cmd file

//          which does not include the PieVectorTable structure.

//###########################################################################

// $TI Release: F28M35x Support Library v110 $

// $Release Date: December 12, 2011 $

//###########################################################################

*/

MEMORY

{

 PAGE 0:    /* Program Memory */

 PAGE 1:    /* Data Memory */

   DEV_EMU             : origin = 0x000880, length = 0x000180     /* device emulation registers */

   CSM                 : origin = 0x000AE0, length = 0x000020       /* code security module registers */

   ADC1_RESULT         : origin = 0x000B00, length = 0x000020     /* ADC1 Results register */

   ADC2_RESULT         : origin = 0x000B40, length = 0x000020     /* ADC2 Results register */

   CPU_TIMER0          : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */

   CPU_TIMER1          : origin = 0x000C08, length = 0x000008     /* CPU Timer1 registers */

   CPU_TIMER2          : origin = 0x000C10, length = 0x000008     /* CPU Timer2 registers */

   PIE_CTRL            : origin = 0x000CE0, length = 0x000020     /* PIE control registers */

   PIE_VECT            : origin = 0x000D00, length = 0x000100     /* PIE Vector Table */

   PIE_VECT_CP         : origin = 0x000E00, length = 0x000100     /* PIE Vector Table Copy */

   DMA                 : origin = 0x001000, length = 0x000200     /* DMA registers */

   ASYSCTRLCONFIG      : origin = 0x001700, length = 0x000080       /* Analog System Control Configuration Registers */

   HWBIST              : origin = 0x001780, length = 0x000040       /* HW BIST Registers    */

   FLASH_REGS          : origin = 0x004000, length = 0x000300     /* Flash Control registers */

   FLASH_ECC           : origin = 0x004300, length = 0x000040     /* Flash/OTP ECC Error Log registers */

   M3PLL               : origin = 0x004400, length = 0x000040       /* M3 PLL Clock Configuration Registers  */

   RAM_REGS            : origin = 0x004900, length = 0x000080     /* RAM Control registers */

   RAM_ERR_REGS        : origin = 0x004A00, length = 0x000080     /* RAM ECC/PARITY/ACCESS Error Log Registers */

   CM_MC_IPC           : origin = 0x004E00, length = 0x000040     /* C28 Control to Master IPC registers */

   MCBSPA              : origin = 0x005000, length = 0x000040     /* McBSP-A registers */

   EPWM1               : origin = 0x005100, length = 0x000080     /* EPWM1 + HRPWM registers */

   EPWM2               : origin = 0x005180, length = 0x000080     /* EPWM2 + HRPWM registers */

   EPWM3               : origin = 0x005200, length = 0x000080     /* EPWM3 + HRPWM registers */

   EPWM4               : origin = 0x005280, length = 0x000080     /* EPWM4 + HRPWM registers */

   EPWM5               : origin = 0x005300, length = 0x000080     /* EPWM5 + HRPWM registers */

   EPWM6               : origin = 0x005380, length = 0x000080     /* EPWM6 + HRPWM registers */

   EPWM7               : origin = 0x005400, length = 0x000080     /* EPWM7 + HRPWM registers */

   EPWM8               : origin = 0x005480, length = 0x000080     /* EPWM8 + HRPWM registers */

   EPWM9               : origin = 0x005500, length = 0x000080     /* EPWM9 registers */

   ECAP1               : origin = 0x005A00, length = 0x000020     /* Enhanced Capture 1 registers */

   ECAP2               : origin = 0x005A20, length = 0x000020     /* Enhanced Capture 2 registers */

   ECAP3               : origin = 0x005A40, length = 0x000020     /* Enhanced Capture 3 registers */

   ECAP4               : origin = 0x005A60, length = 0x000020     /* Enhanced Capture 4 registers */

   ECAP5               : origin = 0x005A80, length = 0x000020     /* Enhanced Capture 5 registers */

   ECAP6               : origin = 0x005AA0, length = 0x000020     /* Enhanced Capture 6 registers */

   EQEP1               : origin = 0x005B00, length = 0x000040     /* Enhanced QEP 1 registers */

   EQEP2               : origin = 0x005B40, length = 0x000040     /* Enhanced QEP 2 registers */

   EQEP3               : origin = 0x005B80, length = 0x000040     /* Enhanced QEP 3 registers */

   GPIOG1CTRL          : origin = 0x005F80, length = 0x000040     /* GPIO control registers */

   GPIOG1DAT           : origin = 0x005FC0, length = 0x000020     /* GPIO data registers */

   GPIOG1TRIP          : origin = 0x005FE0, length = 0x000020     /* GPIO trip/LPM registers */

   COMP1               : origin = 0x006400, length = 0x000020     /* Comparator + DAC 1 registers */

   COMP2               : origin = 0x006420, length = 0x000020     /* Comparator + DAC 2 registers */

   COMP3               : origin = 0x006440, length = 0x000020     /* Comparator + DAC 3 registers */

   COMP4               : origin = 0x006460, length = 0x000020     /* Comparator + DAC 4 registers */

   COMP5               : origin = 0x006480, length = 0x000020     /* Comparator + DAC 5 registers */

   COMP6               : origin = 0x0064A0, length = 0x000020     /* Comparator + DAC 6 registers */

   GPIOG2CTRL          : origin = 0x006F80, length = 0x000040     /* GPIO control registers */

   GPIOG2DAT           : origin = 0x006FC0, length = 0x000020     /* GPIO data registers */

   SYSTEM              : origin = 0x007010, length = 0x000020     /* System control registers */

   SPIA                : origin = 0x007040, length = 0x000010     /* SPI-A registers */\

   SCIA                : origin = 0x007050, length = 0x000010     /* SCI-A registers */

   NMIINTRUPT          : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */

   XINTRUPT            : origin = 0x007070, length = 0x000010     /* external interrupt registers */

   ADC1                : origin = 0x007100, length = 0x000080     /* ADC1 registers */

   ADC2                : origin = 0x007180, length = 0x000080     /* ADC2 registers */

   I2CA                : origin = 0x007900, length = 0x000040     /* I2C-A registers */

   FLASH_EXE_ONLY      : origin = 0x13FFF2, length = 0x000002       /* FLASH execution only locations */

   ECSL_PWL            : origin = 0x13FFF4, length = 0x000004       /* FLASH ECSL password locations  */

   CSM_PWL             : origin = 0x13FFF8, length = 0x000008     /* FLASH CSM password locations.  */

}

In CCSv4.2.5 I had the same problem until I disabled real-time miode. How do I disable real-time mode in CCSv5.2

Thanks,

Pat