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C6678 Device Cycle accurate simulator

Asheesh Bhardwaj
Expert 4680 points
Other Parts Discussed in Thread: TMS320C6678

We are using C6678 Device Cycle accurate simulator for L1/L2 memory similar to the device. The simulator says that it supports core Pac.

Each C66x CorePac of the TMS320C6678 device contains a 512KB level-2 memory (L2), a 32KB level-1 program

memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 4096KB multicore shared memory

(MSM). All memory on the C6678 has a unique location in the memory map.

I donot find the cache and memory map configuration supported by the Device simulator. Where to locate the details on CCS?

Regards

Asheesh

  • 0
    TI__Intellectual 1420 points

    Asheesh,

    The simulator memory map for its modeled IPs will be same as the device h/w. To get a summary of what IPs are modeled in simulator, you can look into CCS target configuration window. Below is the snapshot of the same.

    "Simulates the C6678 device which includes C66x CorePac(8x), MSMC (Multicore Shared Memory Controller), Inter-processor communication, CPINTC(4x), EDMA(3x), TIMER64(16x), Semaphore2,Semaphore2, DDR3 Memory controller and DDR3 memory, GPIO, Queue-manager Sub-system, SRIO and Network coprocessor (Packet Accelerator, Switch Sub-system).This simulator does not model PCIe Sub-system, and PSC (Power and Sleep Controller). This configuration is cycle accurate and hence suitable for applications development and benchmarking. 
 Note on other configurations available for this Device: 
 * There is a corresponding faster configuration (C6678 Device Functional Simulator) in the "Basic Setup", that can be used for applications development and understanding the system behavior, but doesn't support cycle accuracy.">

    For simulator user guide, you can also refer to http://processors.wiki.ti.com/index.php/TCI6616/C6670/TCI6608/C6678/TCI6618_Device_simulator_User_Guide


    For knowing device memory map of the hardware you can refer to http://www.ti.com/lit/gpn/tms320c6678

    In the same document it is mentioned that

    After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be
    reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the
    L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way
    set-associative cache, while L1P is a direct-mapped cache.

    So L1P and L1D is configured as all cache by default which is 32KB on bringup. For L2 on bringup cache size is 0.

    regards,

    Sheshadri

  • 0 in reply to Sheshadri Chakravarthy
    TI__Expert 4680 points

    Thanks Sheshadri.

    Thuis means the L2 cache is not enabled by default. Is there an example code which i can refer to for enabling the L2 cache of 128K or 256K in simulator environment without using BIOS APIs.

    Regards

    Asheesh