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CCSv5.3 debugger, GPIO registers

Valery Venedictov
Prodigy 100 points

Hello.

Here an excerpt from Registers view:

GPIO    

               …….     

               SET_RIS_TRIG   0x00000C00        

                              _RESV   0000000000000000            Reserved             

                              SETRIS_0            0                           

                              SETRIS_1            0                           

                              SETRIS_2            0                           

                              SETRIS_3            0                           

                              SETRIS_4            1 - ENABLE                        

                              SETRIS_5            1 - ENABLE                        

                              SETRIS_6            0                           

                              SETRIS_7            0                           

                              SETRIS_8            0                           

                              SETRIS_9            0                           

                              SETRIS_10          0                           

                              SETRIS_11          0                           

                              SETRIS_12          0                           

                              SETRIS_13          0                           

                              SETRIS_14          0                           

                              SETRIS_15          0                           

I guess there should be SETRIS_10 and SETRIS_11 enabled, not SETRIS_4 and SETRIS_5.

Best regards,

Valery

 

  • 0
    TI__Guru**** 171104 points

    Valery,

    Device used? Is this a value expected after reset? Any additional details?

    --Rafael

  • 0 in reply to desouza
    Prodigy 100 points

    Hello Rafael.

    Device used - C6455.
    My application configures GPIO pins 10 and 11 to generate interrupts and it works.
    Evidently there is an error in the Registers form.
    The value of register SET_RIS_TRIG=0x00000C00 is correct (bits 10 and 11),
    but the values of separate bits are wrong (SETRIS_4 and SETRIS_5).

    Best regards,
    Valery

  • 0 in reply to Valery Venedictov
    TI__Guru**** 171104 points

    Valery,

    Thanks for pointing this; you are correct: the bits are inverted in the file <cslr_gpio.xml> under C:\ti\ccsv5\ccs_base\common\targetdb\Modules - if curious, you can inspect this file under a simple text editor and see that SETRIS_0 starts at position 15 of the SET_RIS_TRIG register bitfield instead of 0. This is similar to other registers of the same GPIO peripheral.

    What is interesting is that this file has not been modified in many years and this issue is probably present there since CCSv3.x.

    I will re-check these files and make the necessary modifications. Any modifications will be available in upcoming releases of CCS and in the device support page.

    Regards,

    Rafael

  • 0 in reply to desouza
    Prodigy 100 points

    I am working with CCS since v2.0 and only now run into this.

    Thanks,

    Valery

  • 0 in reply to Valery Venedictov
    TI__Guru**** 171104 points

    Valery,

    Please unzip the attached file to the directory I specified above; it should correct this issue (I inverted the bit order).

    CCSv2.0 did not support C6455 devices; I confirmed this issue exists in CCSv3.3, as its <cslr_gpio.xml> file is identical to the one present in v5. 

    Regards,

    Rafael

    cslr_gpio.zip