OpenMP in single core vs multi-core

Hi,

A bit addition to my previous post. My RTSC platform is as below:

Inside my .cfg (in the previous post), I created a heap named "ddr_heap" inside DDR3 memory region. Inside this heap I allocate several variables (arrays) (using Memory_alloc) for example S, P, L, and Ss. So, basically all these arrays are in DDR3. In my #pragma omp parallel, I set these arrays as private.

Is this safe? Sorry if this has been questioned and answered before.

I'm guessing this is why when only 1 core is used, no error happened. The exception error happened when more than 1 core are used.

Any response/help is appreciated.

[EDIT: Is this problem related to http://e2e.ti.com/support/embedded/bios/f/355/p/180742/654302.aspx ?]

Rizuan

Hi,

Can anyone help me regarding this issue, please.

Kind regards,

Rizuan

Rizuan, the error message appears to indicate that an overflow is corrupting the text section in MSMCSRAM.

RIZUAN said:

Exception,

Address,0x0c00d110

Decoded,Internal: Opcode exception;

Hi Ajay,

Sorry for the delay. I've been away for some other works. You've been helpful.

I couldn't recreate the same exception error. I just upgrade to the MCSDK 2.1.2.5 and CGT 7.4.2.

Now, I've changed the .text to DDR3 section and received the following exception error:

Exception, Address,0xf0800000 Decoded,Internal: Opcode exception; Exception Context, $addr,0x0084d290 $type,ti.sysbios.family.c64p.Exception.Context A0,0x00000000 A1,0x00000404 A10,0xe6000000 A11,0xfe400000 A12,0xad000000 A13,0x41d23555 A14,0xe3000000 A15,0xc1cff1a3 A16,0x00000000 A17,0x00000000 A18,0x00000000 A19,0x0000003a A2,0x00000000 A20,0x00000039 A21,0x901bab58 A22,0x00000000 A23,0x901bab58 A24,0x00000001 A25,0x8e120c1c A26,0x8e120c1a A27,0x8e120c18 A28,0x8e120c16 A29,0x8e120c14 A3,0x00000038 A30,0x8e120c12 A31,0x000001c8 A4,0x85800000 A5,0xc1cfd535 A6,0x00000208 A7,0x71eff119 A8,0x00000200 A9,0x0c0e6700 AMR,0x00000000 B0,0x00000000 B1,0x00000001 B10,0x59800000 B11,0xc1c0aceb B12,0x30c00000 B13,0x41d00734 B14,0xa02515a0 B15,0x901baf20 B16,0x00104000 B17,0x80000000 B18,0x0000003b B19,0x901bab58 B2,0x901bad28 B20,0x00000000 B21,0x901bab58 B22,0x901bab58 B23,0x00000000 B24,0x00000000 B25,0x00000000 B26,0x8e117ae0 B27,0x00004d00 B28,0x8e117920 B29,0x8e118aa0 B3,0xf0800000 B30,0x0000001c B31,0x00103800 B4,0x00000038 B5,0x41d50852 B6,0x80104820 B7,0x71eff115 B8,0x5421488a B9,0x00000208 EFR,0x00000002 IERR,0x00000008 ILC,0x00000000 IRP,0x0c00eb36 ITSR,0x0000000f NRP,0xf0800000 NTSR,0x0001000f RILC,0x00000001 SSR,0x00000000

How did you know that the previous exception error belongs to the .text section? Is there any documentation that I missed?

Rizuan

Because it says "Opcode exception".  This is presumably an attempt to decode an invalid instruction opcode, and instructions typically reside in the .text section.

Hi Ajay and Archaeologist,

Thanks for your reply and help. It turns out that the reason why I received such exception errors because of the Image Processing Demo example is having issue with CGT 7.4.1 and above as stated here. I created my project based on the example.

After change to CGT 7.4.0, the problem is gone.

I don't have problem when running my SPMD program (I've explained how I create the SPMD program briefly in my first post in this thread) in single and two cores. When I divide the program to run in 4 cores, it hang and sometimes gave exception errors that I attached here at the end of this post. This is my .cfg file. 0552.RKLT_OpenMPv2.1.cfg. And my platform.xdc is as shown below.

As you may notice, my OpenMP.stackRegionId is 2 and the exception error stated that it is Internal: Instruction fetch exception. Why the address is 0x00000000 ? Can anyone here help me about this and maybe other problems that may exists in this configuration and platform files ?

Exception, Address,0x00000000 Decoded,Internal: Instruction fetch exception; Exception Context, $addr,0x0084d360 $type,ti.sysbios.family.c64p.Exception.Context A0,0x00000000 A1,0x00000000 A10,0x00000000 A11,0x00000000 A12,0x00000000 A13,0x40a12200 A14,0x00000000 A15,0x40a14000 A16,0x00000000 A17,0x00000000 A18,0x00000000 A19,0x0000003a A2,0x00000000 A20,0x00000039 A21,0x9023aad8 A22,0x00000000 A23,0x9023aad8 A24,0x00000000 A25,0x8e120c1c A26,0x8e120c1a A27,0x8e120c18 A28,0x8e120c16 A29,0x8e120c14 A3,0x00000038 A30,0x8e120c12 A31,0x000001c8 A4,0x00000000 A5,0x409a6000 A6,0x00000208 A7,0x71effbf5 A8,0x00000200 A9,0x0c0e69c8 AMR,0x00000000 B0,0x00000000 B1,0x00000001 B10,0x00000000 B11,0x40a1ea00 B12,0x00000000 B13,0x40a25800 B14,0xa03215a0 B15,0x9023aea0 B16,0x00104000 B17,0x80000000 B18,0x0000003b B19,0x9023aad8 B2,0x9023aca8 B20,0x00000000 B21,0x9023aad8 B22,0x9023aad8 B23,0x00000000 B24,0x00000000 B25,0x00000000 B26,0x8e117ae0 B27,0x00004d00 B28,0x8e117920 B29,0x8e118aa0 B3,0x00000000 B30,0x0000001c B31,0x00103800 B4,0x00000038 B5,0x4099ec00 B6,0x80104820 B7,0x71effbf1 B8,0x0000067b B9,0x00000208 EFR,0x00000002 IERR,0x00000001 ILC,0x00000000 IRP,0x0c08114c ITSR,0x0000000f NRP,0x00000000 NTSR,0x0001000f RILC,0x00000001 SSR,0x00000000

Many thanks,

Rizuan

Trying to execute address 0x0 indicates a NULL function pointer somewhere in the code.  Are you able to determine what the PC was before this exception?

C6000 compiler version 7.4.1 should add only bug fixes to 7.4.0; if 7.4.0 is working for you, it is unlikely to be a bug that was introduced in 7.4.1.  More likely, 7.4.1 does something slightly different that happens to trigger a bug that was already in either your code or some part of the toolchain.

With regards to the configuration, I don't know; I am not an expert in that area.

Probably not related to your issue - In your cfg file, you set "OpenMP.enableMemoryConsistency = false;". This implies that you will manage cache consistency for shared variables manually by inserting Cache invalidate calls at the appropriate points in your program. Any specific reason you disabled the memory consistency feature in the OMP runtime?

One more thing - have you been able to get some of the simpler examples, such as matrix multiplication to work across 8 cores in your OpenMP environment?

Ajay

Hi everyone,

Thanks for the replies.

Ajay Jayaraj said:

have you been able to get some of the simpler examples, such as matrix multiplication to work across 8 cores in your OpenMP environment?

Yes. I used the code from OMP Examples->C6678 Examples->OpenMP matrix vector multiplication example, into my project, using the configuration file and platform.xdc that I show before by using 8 cores. It returned the same result as the example.

Ajay Jayaraj said:

Any specific reason you disabled the memory consistency feature in the OMP runtime?

Unfortunately, I don't. I just follow what is there in the configuration file from the image processing example by TI. I've set it to true now but it give the same problem when using 4 cores or more.

Archaeologist said:

Are you able to determine what the PC was before this exception?

No. But I will do that later.

At this point, I think it is necessary for me to show my code, at least the omp pragma part because it is lengthy. Here it is:

This is the output from console when using only 1 core:

And this is the output if using 2 cores:

And finally 4 cores:

We can notice that in the 4 cores execution, it ignores the second #pragma omp critical, marked by "Begin Applying P,L,U,S". It doesn't wait for all the cores to finish executing the previous lines as in the 2 cores execution. This is what I suspect.

Can anyone comment on this or any other solutions?

Many thanks, guys.

Rizuan

Hi Archaeologist,

Suddenly you've made me confuse since I'm also a beginner in OpenMP =D. Then I realised that I've used the same approach on Visual C++ OpenMP 2.0 and also by using Intel Compiler OpenMP 3.0. Actually my project in CCS now is from the desktop implementation that I've created before, and that was my first time using OpenMP.

You can refer to this pdf file at page 23. Threads wait their turn - only one at a time call the function inside the critical region.

Kind regards,

Rizuan

Hi Archaeologist,

When read again your question, I think you are right. I've no idea now how to troubleshoot the problem. I just suspect that is the problem.

P/S: That was a good question though.

Rizuan

I believe the fact that you've demonstrated it successfully multithreading with 2 cores, and failing with 4, is an important observation.