• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 55 subscribers
  • Views 1540 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How do I execute a program from internal SRAM (L2 cache) using CCS on DM8168?

_Ralph_
Guru 10685 points

I'm using the latest CCS to debug my DM8168 using a USB XDS560v2 emulator and would like to run a program from the internal SRAM. I have 2 questions regarding this:

1) What memory address does CCS copy a program to when you run "Load program"?

2) How can I get CCS to load a program directly to internal SRAM (L2 cache) and load it from there?

Grateful for any advice. I'm trying to debug a faulty connection to my DDR RAM chips so obviously I don't want CCS to go loading my test program into main memory.

Thanks,
Ralph

  • 0
    TI__Guru**** 480781 points

    Hi Ralph,

    _Ralph_ said:
    1) What memory address does CCS copy a program to when you run "Load program"?

    CCS will look at the debug symbols to determine where to load the sections of your program to what memory location

    You can see what there memory regions yourself by looking at the generate map file (*.map) that is located in the same location as the *.out file

    You can control where your sections of code are allocated to which memory location with your linker command file (*.cmd) that is associated with your project

    _Ralph_ said:
    2) How can I get CCS to load a program directly to internal SRAM (L2 cache) and load it from there?

    Modify your linker command file (*.cmd) to place all your code in internal SRAM

    If all of these concepts are new to you, I suggest you look at the below wiki topic for a primer on how linker command files work, especially the section for Code Generation Tools:

    http://processors.wiki.ti.com/index.php/Troubleshooting_CCS_-_Data_Verification_Errors

    Hope this helps

    ki

  • 0 in reply to Ki
    Guru 10685 points

    Hi Ki,

    That was a really great reply, thanks. I think I understand it now.

    How do I configure the L2 cache as SRAM and not cache? I can't see anything under "Advanced options" in CCS.

    Thanks,
    Ralph

  • 0 in reply to _Ralph_
    TI__Guru**** 480781 points

    _Ralph_ said:
    How do I configure the L2 cache as SRAM and not cache? I can't see anything under "Advanced options" in CCS.

    You probably can do this via some target initialization via GEL. This is more of a device specific question, not tools. I would post your query under the DM816x forums.

    Thanks

    ki

  • 0 in reply to Ki
    Guru 10685 points

    Okay thanks for that. I'll modify the default GEL.

  • 0 in reply to _Ralph_
    Intellectual 670 points

    Ralph, 

    Please let us know how it works. 

    In CCS3.3 for 6437 for example, you can set that in CCS. Now dealing with DM8127, I  am also a bit lost on where to configure SRAM for L2 or L1. My guess is in either GEL or  some configure file for DSP. 

    Thanks