• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 53 subscribers
  • Views 917 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Load individual .out file

Rudolph Raab
Intellectual 760 points
Other Parts Discussed in Thread: OMAPL138

I used Simulink R2012b to generate and compile an embedded target project for an OMAP-138 EVM. This worked fine-- no errors. However all I'm left with is a bunch of source and header files, supporting files (linker stuff, memory maps, etc) and a .out file. Is there any way to load this .out file onto the OMAP and run it? Doing so from inside Simulink would be great, but I'll be happy with just getting it running on the board.

  • 0
    TI__Guru**** 463901 points

    Rudolph Raab said:
    Is there any way to load this .out file onto the OMAP and run it?

    You can use CCS for this (assuming you have a copy of CCS)

    Rudolph Raab said:
    Doing so from inside Simulink would be great

    If you have CCS version 3.x, you can do this from Simulink. The Simulink integration with newer CCS versions is not supported (yet)

    Rudolph Raab said:
    but I'll be happy with just getting it running on the board.

    Check out the CCS resource for the version you have:

    http://processors.wiki.ti.com/index.php/Category:CCS

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 760 points

    I'm sorry, I can't find anything about what I'm trying to do in the link you gave me. I know how to debug a project with CCS v5, but I only have a .out file in this case. I would appreciate more specific guidance.

  • 0 in reply to Rudolph Raab
    TI__Guru**** 463901 points

    What you wish to do is to start a "project-less" debug session and manually load your out file. There is a video that demonstrates this:

    http://software-dl.ti.com/sdo/sdo_apps_public_sw/CCSv4/Demos/Manual_launch_of_target_configuration_shared/Manual_launch_of_target_configuration_shared.htm

    The video is for an older version of CCS but the concept is the same in v5.

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 760 points

    Thank for your video link. I was able to open a debug configuration from a previous CCS project for the OMAP, and load Simulink's .out file. However when doing so I get the following error:

    C674X_0: File Loader: Data verification failed at address 0xC3100000  
    Please verify target memory and memory map.
    C674X_0: GEL: File:  
    C:\Users\ee_admin\Documents\OMAPL138_AudioDelay_ticcs\OMAPL138_AudioDelay_ticcs\CustomMW\OMAPL138_AudioDelay.out: a data verification error occurred, file load  
    failed.

    I have attached the linker address map and linker command file that Simulink used, if that helps. 

    Fullscreen 5618.OMAPL138_AudioDelaycfg.cmd.txt Download 
    /*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT OMAPL138_AudioDelay.cdb */

/* MODULE PARAMETERS */
-u _targetInitialize
GBL_USERINITFXN = _targetInitialize;

-u DDR
MEM_SEGZERO = DDR;
-u DDR
MEM_MALLOCSEG = DDR;

-u _CLK_gethtime
CLK_TIMEFXN = _CLK_gethtime;
-u HWI_F_dispatch
CLK_HOOKFXN = HWI_F_dispatch;

-u _KNL_tick
PRD_THOOKFXN = _KNL_tick;

-u IRAM
RTDX_DATAMEMSEG = IRAM;

-u IRAM
HST_DSMBUFSEG = IRAM;

-u GBL_NULL
SWI_EHOOKFXN = GBL_NULL;
-u GBL_NULL
SWI_IHOOKFXN = GBL_NULL;
-u SWI_F_exec
SWI_EXECFXN = SWI_F_exec;
-u SWI_F_run
SWI_RUNFXN = SWI_F_run;

-u DDR
TSK_STACKSEG = DDR;
-u _FXN_F_nop
TSK_VCREATEFXN = _FXN_F_nop;
-u _FXN_F_nop
TSK_VDELETEFXN = _FXN_F_nop;
-u _FXN_F_nop
TSK_VEXITFXN = _FXN_F_nop;

-u GBL_NULL
IDL_CALIBRFXN = GBL_NULL;

-u _UTL_doAbort
SYS_ABORTFXN = _UTL_doAbort;
-u _UTL_doError
SYS_ERRORFXN = _UTL_doError;
-u _exitprocessing
SYS_EXITFXN = _exitprocessing;
-u _UTL_doPutc
SYS_PUTCFXN = _UTL_doPutc;

-u _FXN_F_nop
GIO_CREATEFXN = _FXN_F_nop;
-u _FXN_F_nop
GIO_DELETEFXN = _FXN_F_nop;
-u _FXN_F_nop
GIO_PENDFXN = _FXN_F_nop;
-u _FXN_F_nop
GIO_POSTFXN = _FXN_F_nop;

-u _FXN_F_nop
PWRM_PWRM_SLOTHOOKFXN = _FXN_F_nop;
-u _FXN_F_nop
PWRM_PWRM_SHAREDRESOURCEFXN = _FXN_F_nop;

/* OBJECT ALIASES */
_CACHE_L2 = CACHE_L2;
_CACHE_L1P = CACHE_L1P;
_CACHE_L1D = CACHE_L1D;
_IRAM = IRAM;
_L3_CBA_RAM = L3_CBA_RAM;
_DDR = DDR;
_PRD_clock = PRD_clock;
_timer1PRD = timer1PRD;
_HWI_RESET = HWI_RESET;
_HWI_NMI = HWI_NMI;
_HWI_RESERVED0 = HWI_RESERVED0;
_HWI_RESERVED1 = HWI_RESERVED1;
_HWI_INT4 = HWI_INT4;
_HWI_INT5 = HWI_INT5;
_HWI_INT6 = HWI_INT6;
_HWI_INT7 = HWI_INT7;
_HWI_INT8 = HWI_INT8;
_HWI_INT9 = HWI_INT9;
_HWI_INT10 = HWI_INT10;
_HWI_INT11 = HWI_INT11;
_HWI_INT12 = HWI_INT12;
_HWI_INT13 = HWI_INT13;
_HWI_INT14 = HWI_INT14;
_HWI_INT15 = HWI_INT15;
_EVENT4 = EVENT4;
_EVENT5 = EVENT5;
_EVENT6 = EVENT6;
_EVENT7 = EVENT7;
_EVENT8 = EVENT8;
_EVENT9 = EVENT9;
_EVENT10 = EVENT10;
_EVENT11 = EVENT11;
_EVENT12 = EVENT12;
_EVENT13 = EVENT13;
_EVENT14 = EVENT14;
_EVENT15 = EVENT15;
_EVENT16 = EVENT16;
_EVENT17 = EVENT17;
_EVENT18 = EVENT18;
_EVENT19 = EVENT19;
_EVENT20 = EVENT20;
_EVENT21 = EVENT21;
_EVENT22 = EVENT22;
_EVENT23 = EVENT23;
_EVENT24 = EVENT24;
_EVENT25 = EVENT25;
_EVENT26 = EVENT26;
_EVENT27 = EVENT27;
_EVENT28 = EVENT28;
_EVENT29 = EVENT29;
_EVENT30 = EVENT30;
_EVENT31 = EVENT31;
_EVENT32 = EVENT32;
_EVENT33 = EVENT33;
_EVENT34 = EVENT34;
_EVENT35 = EVENT35;
_EVENT36 = EVENT36;
_EVENT37 = EVENT37;
_EVENT38 = EVENT38;
_EVENT39 = EVENT39;
_EVENT40 = EVENT40;
_EVENT41 = EVENT41;
_EVENT42 = EVENT42;
_EVENT43 = EVENT43;
_EVENT44 = EVENT44;
_EVENT45 = EVENT45;
_EVENT46 = EVENT46;
_EVENT47 = EVENT47;
_EVENT48 = EVENT48;
_EVENT49 = EVENT49;
_EVENT50 = EVENT50;
_EVENT51 = EVENT51;
_EVENT52 = EVENT52;
_EVENT53 = EVENT53;
_EVENT54 = EVENT54;
_EVENT55 = EVENT55;
_EVENT56 = EVENT56;
_EVENT57 = EVENT57;
_EVENT58 = EVENT58;
_EVENT59 = EVENT59;
_EVENT60 = EVENT60;
_EVENT61 = EVENT61;
_EVENT62 = EVENT62;
_EVENT63 = EVENT63;
_EVENT64 = EVENT64;
_EVENT65 = EVENT65;
_EVENT66 = EVENT66;
_EVENT67 = EVENT67;
_EVENT68 = EVENT68;
_EVENT69 = EVENT69;
_EVENT70 = EVENT70;
_EVENT71 = EVENT71;
_EVENT72 = EVENT72;
_EVENT73 = EVENT73;
_EVENT74 = EVENT74;
_EVENT75 = EVENT75;
_EVENT76 = EVENT76;
_EVENT77 = EVENT77;
_EVENT78 = EVENT78;
_EVENT79 = EVENT79;
_EVENT80 = EVENT80;
_EVENT81 = EVENT81;
_EVENT82 = EVENT82;
_EVENT83 = EVENT83;
_EVENT84 = EVENT84;
_EVENT85 = EVENT85;
_EVENT86 = EVENT86;
_EVENT87 = EVENT87;
_EVENT88 = EVENT88;
_EVENT89 = EVENT89;
_EVENT90 = EVENT90;
_EVENT91 = EVENT91;
_EVENT92 = EVENT92;
_EVENT93 = EVENT93;
_EVENT94 = EVENT94;
_EVENT95 = EVENT95;
_EVENT96 = EVENT96;
_EVENT97 = EVENT97;
_EVENT98 = EVENT98;
_EVENT99 = EVENT99;
_EVENT100 = EVENT100;
_EVENT101 = EVENT101;
_EVENT102 = EVENT102;
_EVENT103 = EVENT103;
_EVENT104 = EVENT104;
_EVENT105 = EVENT105;
_EVENT106 = EVENT106;
_EVENT107 = EVENT107;
_EVENT108 = EVENT108;
_EVENT109 = EVENT109;
_EVENT110 = EVENT110;
_EVENT111 = EVENT111;
_EVENT112 = EVENT112;
_EVENT113 = EVENT113;
_EVENT114 = EVENT114;
_EVENT115 = EVENT115;
_EVENT116 = EVENT116;
_EVENT117 = EVENT117;
_EVENT118 = EVENT118;
_EVENT119 = EVENT119;
_EVENT120 = EVENT120;
_EVENT121 = EVENT121;
_EVENT122 = EVENT122;
_EVENT123 = EVENT123;
_EVENT124 = EVENT124;
_EVENT125 = EVENT125;
_EVENT126 = EVENT126;
_EVENT127 = EVENT127;
_KNL_swi = KNL_swi;
_PRD_swi = PRD_swi;
_TSK_idle = TSK_idle;
_initTerminateTSK = initTerminateTSK;
_tBaseRateTSK = tBaseRateTSK;
_LOG_system = LOG_system;
_rtClockSEM = rtClockSEM;
_stopSEM = stopSEM;
_startSEM = startSEM;

/* MODULE GBL */

SECTIONS {
   .vers (COPY): {} /* version information */
}

-priority
--trampolines
-llnknone.a674
-ldrivers.a674         /* device drivers support */
-lsioboth.a674         /* supports both SIO models */
-lbios6748.a674        /* BIOS clock specific library */
-lbios.a674            /* DSP/BIOS support */
-lrts6740.lib          /* C and C++ run-time library support */


_GBL_CACHE = GBL_CACHE;
_BCACHE_bootInit=_BCACHE_setCacheToSram;

/* MODULE MEM */
-stack 0x2000
MEMORY {
   CACHE_L2    : origin = 0x11820000,  len = 0x20000
   CACHE_L1P   : origin = 0x11e00000,  len = 0x8000
   CACHE_L1D   : origin = 0x11f00000,  len = 0x8000
   IRAM        : origin = 0x11800000,  len = 0x20000
   L3_CBA_RAM  : origin = 0x80000000,  len = 0x20000
   DDR         : origin = 0xc3000000,  len = 0x1000000
}
/* MODULE CLK */
SECTIONS {
   .clk: {
        *(.clk) 
   } > IRAM, RUN_START(CLK_A_TABBEG) 
}
_CLK_PRD = CLK_PRD;
_CLK_COUNTSPMS = CLK_COUNTSPMS;
_CLK_REGS = CLK_REGS;
_CLK_USETIMER = CLK_USETIMER;
_CLK_TIMERNUM = CLK_TIMERNUM;
_CLK_TDDR = CLK_TDDR;

/* MODULE PRD */
SECTIONS {
   .prd: RUN_START(PRD_A_TABBEG), RUN_END(PRD_A_TABEND) {
   } > IRAM
}
PRD_A_TABLEN = 1;

_HWI_CFGDISPATCHED = HWI_CFGDISPATCHED;

/* MODULE SWI */
SECTIONS {
   .swi: RUN_START(SWI_A_TABBEG), RUN_END(SWI_A_TABEND) {
   } > IRAM
}
SWI_A_TABLEN = 2;

/* MODULE TSK */
SECTIONS {
   .tsk: {
        *(.tsk) 
   } > IRAM
}

/* MODULE IDL */
SECTIONS {
   .idl: {
        *(.idl) 
   } > IRAM, RUN_START(IDL_A_TABBEG)
   
   .idlcal: {
        *(.idlcal) 
   } > IRAM, RUN_START(IDL_A_CALBEG) 
}


LOG_A_TABLEN = 1; _LOG_A_TABLEN = 1;

PIP_A_TABLEN = 0;


SECTIONS {
        .bss:     {} > DDR

        .far:     {} > DDR

        .sysdata: {} > DDR

        .udev: {} > DDR

        frt:    {} > DDR

        .mem: 	  {} > DDR

        .cio:     {} > DDR

        .data:    {} > DDR

        .gio:     {} > DDR

        .pinit:   {} > DDR

        .sys:     {} > DDR

        .sysregs: {} > DDR

        .text:    {} > DDR

        .cinit:    {} > DDR

        .devtable: {} > DDR

        .switch:    {} > DDR

        .gblinit:    {} > DDR

        .sysinit:    {} > DDR

        .trcdata:    {} > DDR

        GROUP {
         .const: align = 0x8 {} 
         .printf (COPY): {} 
        } > DDR

        .args: align=4 fill=0 {
            *(.args)
            . += 0x4;
        } > DDR

        .DDR$heap: {
            . += 0x100000;
        } RUN_START(DDR$B), RUN_START(_DDR_base), RUN_SIZE(DDR$L), RUN_SIZE(_DDR_length) > DDR

        .hwi_vec: {
            *(.hwi_vec)
        } align = 0x400, RUN_START(HWI_A_VECS) > IRAM

        .dsm: {} > IRAM

        .sem: {} > IRAM

        .bios:    {} > IRAM

        .pmonchip: {} > IRAM

        .hwi: {}  > IRAM

        .TSK_idle$stk: {
            *(.TSK_idle$stk)
        } > IRAM

        .initTerminateTSK$stk: {
            *(.initTerminateTSK$stk)
        } > IRAM

        .tBaseRateTSK$stk: {
            *(.tBaseRateTSK$stk)
        } > IRAM

        /* LOG_system buffer */
        .LOG_system$buf: align = 0x100 {} > IRAM

        .trace: fill = 0x0  align = 0x4 {
           _SYS_PUTCBEG = .;
           . += 0x200;
           _SYS_PUTCEND = . - 1;
        } > IRAM

        .hst: RUN_START(HST_A_TABBEG), RUN_START(_HST_A_TABBEG), RUN_END(HST_A_TABEND), RUN_END(_HST_A_TABEND) {
        } > IRAM

        .log: RUN_START(LOG_A_TABBEG), RUN_START(_LOG_A_TABBEG), RUN_END(LOG_A_TABEND), RUN_END(_LOG_A_TABEND) {
        } > IRAM

        .pip: RUN_START(PIP_A_TABBEG), RUN_START(_PIP_A_TABBEG), RUN_END(PIP_A_TABEND), RUN_END(_PIP_A_TABEND) {
        } > IRAM

        .sts: RUN_START(STS_A_TABBEG), RUN_START(_STS_A_TABBEG), RUN_END(STS_A_TABEND), RUN_END(_STS_A_TABEND) {
        } > IRAM

        .stack: align = 0x8 {
            GBL_stackbeg = .;
            *(.stack)
            GBL_stackend = GBL_stackbeg + 0x2000 - 1;
            _HWI_STKBOTTOM = GBL_stackbeg + 0x2000 - 8;
            _HWI_STKTOP = GBL_stackbeg;
        } > IRAM

}

    5732.OMAPL138_AudioDelay.map.txt

  • 0 in reply to Rudolph Raab
    TI__Guru**** 463901 points

    Thank you for attaching the the map file and linker command file. That is but part of the equation when trying to resolve data verification errors. Please also check your debugger memory map and available target memory. See the below troubleshooting guide for more information:

    http://processors.wiki.ti.com/index.php/Troubleshooting_CCS_-_Data_Verification_Errors

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 760 points

    I looked at the debugger memory map in CCS and it only had one entry and no specified GEL files to read from. So I pointed it at one from LogicPD's BSL which cleared out 0xC0000000 through to 0xDFFFFFFF with the attributes "R|W|AS4". Still get the same data verification error, and at the same address. I think the issue may be on Matlab's end, using the wrong linker command file. I know the command checkEnvSetup asks for LogicPD's BSL, and when given the correct location will silently fail to recognize it.

  • 0 in reply to Rudolph Raab
    TI__Guru**** 463901 points

    Also check to see if the target memory has been initialized properly. That is the last step in the wiki:

    http://processors.wiki.ti.com/index.php/Troubleshooting_CCS_-_Data_Verification_Errors#Available_Target_Memory

    I believe address 0xc0000000 is external RAM and needs to be initialized. There should be some GEL functions to initialize the target and external memory. Make sure they are being run.

  • 0 in reply to Ki
    Intellectual 760 points

    You're right, it had to be initialized. I thought it was automatic; part of OnTargetConnect. But I saw a few other functions called "hotmenus" in the GEL file, with a few core frequency and mDDR initialization routines. It took me a while to find them in CCS, hiding under the "scripts" menu. I used one and then Simulink's .out file loaded and ran fine (I think it ran OK, the Simulink model needs some adjusting).

    Thank you for all your help. Now that this issue has been resolved, I'll verify your answer to my original question.