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Hello,
I have some code which uses EDMA to do dsp-to-dsp communication. When running the code in the CCS simulator (C6678), the message "Warning: Write operation not permitted since EDMA is disabled" always pops up and the code does not operate EVM correctly. However, the very same code runs fine with the hardware (C6678 EVM) without any hiccups.
I was wondering if the support of EDMA in CCS simulator (C6678) needs some special set-up or licenses. Any pointers?
Thanks.
Weihua
Hi Weihua,
Can you give us below information to better analyse the problem,
1. Which CCS/simulator version are you using? Is it CCS4.x or CCS5.1, CCS5.2, CCS5.3?
2. Which simulator configuration are you using for C6678? Is it functional or Cycle Approximate simulator?
3. Can you share the config files tisim_c6678_pv.cfg and tisim_c6678_cx.cfg - from <ccs install>\ccs_base\simulation_csp_kesytone1\bin\configurations. Alternately you can infer the path from CCS Target configurations-->Adavanced Tab --> and click on the DSP processor name "TMS320C66x_0" and look for config file in teh right pane.
regards,
Sheshadri
Hi Sheshadri,
| 1. Which CCS/simulator version are you using? Is it CCS4.x or CCS5.1,
CCS5.2, CCS5.3?
CCS 5.3.0.00090
2. Which simulator configuration are you using for C6678? Is it
functional or Cycle Approximate simulator?
C6678 Device Functional Simulator, Little Endian
3. Can you share the config files tisim_c6678_pv.cfg and
tisim_c6678_cx.cfg - from<ccs
install>\ccs_base\simulation_csp_kesytone1\bin\configurations.
Alternately you can infer the path from CCS Target
configurations-->Adavanced Tab --> and click on the DSP processor name
"TMS320C66x_0" and look for config file in teh right pane.
See Attachment
Hi Sheshadri,
The config file is pasted below:
// C6657 Platform Functional Simulator Configuration File
// Copyright (c) 2007-2008 Texas Instruments Incorporated
// Version 0.0.1//--------------------------------------------------------------------------------
MODULE GTI_INFO;
GTI_DVR_NAME tisim_adv_sb.dvr;
SERVER_AUTO_RUN ON;
END GTI_INFO;
MODULE SIMBRIDGE;
ADVANCE_TYPE CYCLE_ADVANCE_WITH_INSTR_HALT;
//
// To enable simulator construction logs uncomment MODULE SIMBRIGE, END SIMBRIDGE and the line having "FILE_LOG ON"
// The options here are
// 1. ON - will generate the default log files, declare_intf.log, connect_intf.log and sim_integration.log
// 2. <file name> - will generate all the log information into the specified file name.
// 3. OFF - logging disabled
//
FILE_LOG ON;
// Send global break status to GTIs of the processors
// that are forced to halt on other processor break point
SEND_GLOBAL_BREAK_STATUS ON;
SIMBRIDGE_DLL ../../../bin/components/sim_server.so;
END SIMBRIDGE;
MODULE BUS_DESCRIPTORS;
STD_BUS_HEADERS1 ../../../bin/configurations/tisim_buses.cfg;
END BUS_DESCRIPTORS;
MODULE System;
DEBUGVIEW CPU0,CPU1;
SUB_MODULES C66XX_N;
MODULE C66XX_N;
SUB_MODULES CPU_SYSTEM_0, CPU_SYSTEM_1, SHARED_SYSTEM_INTF,
SHARED_SYSTEM;
MODULE CPU_SYSTEM_0;
SUB_MODULES CPU0, CGEM_SSI_0;
MODULE CPU0;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 0;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE0;
IMPORT PATCH0;
END CPU0;
MODULE CGEM_SSI_0;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU0;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 0;
NUM_MM 4;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x100000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 0;
PRIV_ID 0; //<CHECK>
SECURE_MODE 1;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 1MB;
MEMORY_SIZE 0x100000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_0;
// security mode change connect
CONNECT1 CPU0.security_mode_in, CGEM_SSI_0.secure_status_opin;
END CPU_SYSTEM_0;
MODULE CPU_SYSTEM_1;
SUB_MODULES CPU1, CGEM_SSI_1;
MODULE CPU1;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 1;
MODULE EFI;
FIFO_LEN_A 6;
FIFO_LEN_B 6;
END EFI;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE1;
IMPORT PATCH1;
END CPU1;
MODULE CGEM_SSI_1;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU1;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 1;
NUM_MM 4;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x100000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 1;
PRIV_ID 1; //<CHECK>
SECURE_MODE 1;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
CACHE_SIZE 0x000000;
MAX_CACHE_SIZE 1MB;
MEMORY_SIZE 0x100000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_1;
// security mode change connect
CONNECT1 CPU1.security_mode_in, CGEM_SSI_1.secure_status_opin;
END CPU_SYSTEM_1;
MODULE SHARED_SYSTEM_INTF;
TYPE SHARED;
SSI_VER SC_1.0.0;
CLOCK_FREQ 1000;
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
DLL ../../../bin/components/sim_shared_system_intf.so;
INIT_FUNC shared_system_intf_init_func;
INIT_DONE_FUNC shared_system_intf_init_done_func;
QUIT_FUNC shared_system_intf_quit_func;
END SHARED_SYSTEM_INTF;
MODULE SHARED_SYSTEM;
SUB_MODULES
INTERCONNECT,
MSMC,
MEMTR_MSMC_Adaptor,
MEMTR_FLATMEM_36BIT_Adaptor, //for ARM DDR access
MEMTR_CGEM0_Slv_Adaptor,
MEMTR_CGEM1_Slv_Adaptor,
TIMER64_0, //Watch Dog for Core0
TIMER64_1, //Watch Dog for Core1
TIMER64_2, //Watch Dog for Core2
TIMER64_3, //Watch Dog for Core3
TIMER64_4,
TIMER64_5,
TIMER64_6,
TIMER64_7,
EDMA,
CP_INTC0,
CP_INTC1,
CP_INTC2,
VCP2_0,
VCP2_1,
SEMAPHORE,
TCP3D_A,
IPC,
GPIO,
QUEUE_MANAGER,
CDMA_INFRA,
INTD_TCP3D_A,
PCIE,
FLATMEM_36BIT, //DDR data model
PSC,
SRIO, //!SRIO sub-system
CDMA_SRIO,
SSI2SOCK_PORT0, //for SRIO
UART_0,
UART_1,
DSP_BOOT_ROM,
Endianess_Adaptor,
Endianess_Adaptor1,
BOOT_CONFIG;
MODULE Endianess_Adaptor;
NAME Endianess_Adaptor;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/o2v_a8_bridge_ssi.so;
INIT_FUNC init_o2v_a8_bridge_intf;
INIT_DONE_FUNC init_done_o2v_a8_bridge_intf;
QUIT_FUNC quit_o2v_a8_bridge_intf;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 EN_WORD_SWAP, 1;
INPUT3 EN_ADDR_SWAP, 0; //Reset value
INPUT4 BIG_ENDIAN, 0;
// UART0
INPUT5 BEG_WS_REG0, 0x02540000;
INPUT6 END_WS_REG0, 0x02540FFF;
END USER_INPUTS;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_0.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_in_read;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_0.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_in_write;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_0.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_in_dbg_read;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_0.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_in_dbg_write;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.UART_0.memtr_read_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_out_read;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.UART_0.memtr_write_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_out_write;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.UART_0.memtr_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_out_dbg_read;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.UART_0.memtr_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.mbus_out_dbg_write;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.reset_in, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT10 System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor.big_endian_in, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian;
END INTERFACES;
END Endianess_Adaptor;
MODULE Endianess_Adaptor1;
NAME Endianess_Adaptor1;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/o2v_a8_bridge_ssi.so;
INIT_FUNC init_o2v_a8_bridge_intf;
INIT_DONE_FUNC init_done_o2v_a8_bridge_intf;
QUIT_FUNC quit_o2v_a8_bridge_intf;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 EN_WORD_SWAP, 1;
INPUT3 EN_ADDR_SWAP, 0; //Reset value
INPUT4 BIG_ENDIAN, 0;
// UART1
INPUT5 BEG_WS_REG0, 0x02550000;
INPUT6 END_WS_REG0, 0x02550FFF;
END USER_INPUTS;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_1.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_in_read;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_1.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_in_write;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_1.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_in_dbg_read;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_1.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_in_dbg_write;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.UART_1.memtr_read_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_out_read;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.UART_1.memtr_write_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_out_write;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.UART_1.memtr_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_out_dbg_read;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.UART_1.memtr_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.mbus_out_dbg_write;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.reset_in, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT10 System.C66XX_N.SHARED_SYSTEM.Endianess_Adaptor1.big_endian_in, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian;
END INTERFACES;
END Endianess_Adaptor1;
////////////////////////////////////////////////////////////////
//////////FLAT MEMORY: COMMON //////////////////////////////////
////////////////////////////////////////////////////////////////
MODULE DSP_BOOT_ROM;
DLL ../../../bin/components/sim_memtr_adaptor.so;
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
SSI_VER SC_1.0.0;
TERMINAL MT_SSI2FLATMEM;
TYPE SHARED;
BUSCONNECT1 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.DSP_BOOT_ROM.MT_SSI2FLATMEM., System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.DSP_BOOT_ROM.;
END DSP_BOOT_ROM;
MODULE UART_0;
NAME UART_0;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ./../../../bin/components/tisim_uartconsole_pv.so;
INIT_FUNC UART_init;
INIT_DONE_FUNC UART_init_done;
QUIT_FUNC UART_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.UART_0.console_clk, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_bit_ack_out;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.UART_0.recv_uart, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_tx_byte_data_out;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.UART_0.get_lcr, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_console_lcr_out;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.UART_0.consolekeypress, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_rx_byte_data_in;
CONNECT5 System.Shared_System.hps_scheduler, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_infra_scheduler;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.UART_0.uart_resp_loop_back_memtr , System.C66XX_N.SHARED_SYSTEM.UART_0.uart_read_response_out;
CONNECT7 System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_error_opin;
CONNECT8 System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi, System.C66XX_N.SHARED_SYSTEM.UART_0.uart_error_opin;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 IP_NAME, UART_0;
INPUT2 PORT_REG_OFFSET, 0x7C; // this is default value;
INPUT3 ALIGNMENT_PARAM, 4; // this is default value;
INPUT4 PID, 0x44141102; //as per GAUSS spec
INPUT5 VERSION, 1.2;
INPUT6 IP, 127.0.0.1;
INPUT7 PORT, 8000;
END USER_INPUTS;
END UART_0;
MODULE UART_1;
NAME UART_1;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ./../../../bin/components/tisim_uartconsole_pv.so;
INIT_FUNC UART_init;
INIT_DONE_FUNC UART_init_done;
QUIT_FUNC UART_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.UART_1.console_clk, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_bit_ack_out;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.UART_1.recv_uart, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_tx_byte_data_out;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.UART_1.get_lcr, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_console_lcr_out;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.UART_1.consolekeypress, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_rx_byte_data_in;
CONNECT5 System.Shared_System.hps_scheduler, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_infra_scheduler;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.UART_1.uart_resp_loop_back_memtr, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_read_response_out;
CONNECT7 System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_error_opin;
CONNECT8 System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi, System.C66XX_N.SHARED_SYSTEM.UART_1.uart_error_opin;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 IP_NAME, UART_1;
INPUT2 PORT_REG_OFFSET, 0x7C; // this is default value;
INPUT3 ALIGNMENT_PARAM, 4; // this is default value;
INPUT4 PID, 0x44141102; //as per GAUSS spec
INPUT5 VERSION, 1.2;
INPUT6 IP, 127.0.0.1;
INPUT7 PORT, 8001;
END USER_INPUTS;
END UART_1;
MODULE BOOT_CONFIG;
NAME BOOT_CONFIG;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ./../../../bin/components/bootconfig_ssi.so;
INIT_FUNC init_bootconfig_intf;
INIT_DONE_FUNC init_done_bootconfig_intf;
QUIT_FUNC quit_bootconfig_intf;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.BOOT_CONFIG.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.mbus_in_read;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.BOOT_CONFIG.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.mbus_in_write;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.BOOT_CONFIG.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.mbus_in_dbg_read;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.BOOT_CONFIG.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.mbus_in_dbg_write;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.reset_in, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.little_endian_in, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.errmsg, System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.BOOT_CONFIG.errmsg, System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 PID, 0x4e840000;
INPUT3 SOC, GAUSS;
END USER_INPUTS;
END BOOT_CONFIG;
MODULE INTERCONNECT;
NAME GAUSS_INTERCONNECT;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_sf_ivahd_interconnect_ssi.so;
INIT_FUNC ivahd_ic_ocp_init;
INIT_DONE_FUNC ivahd_ic_ocp_init_done;
QUIT_FUNC ivahd_ic_ocp_quit;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 CFG_FILE, ../../../bin/configurations/tisim_l3_c6657.cfg;
END USER_INPUTS;
MODULE INTERFACES;
//INTERCONNECT TO Reset SIGNAL
CONNECT1 System.C66XX_N.SHARED_SYSTEM_INTF.reset_out, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.receive_reset;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.error_opin,System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.error_opin,System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi;
//CONNECT4 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.ccs_error_q,System.Shared_System.hps_error_q;
END INTERFACES;
END INTERCONNECT;
MODULE MSMC;
NAME msmc;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_msmc_ssi.so;
INIT_FUNC msmc_ssi_init_func;
INIT_DONE_FUNC msmc_ssi_init_done_func;
QUIT_FUNC msmc_ssi_quit_func;
NO_OF_CORES 2;
RAM_START_ADDRESS 0x0C000000;
RAM_SIZE 0x100000;
CFG_START_ADDRESS 0x0BC00000;
END MSMC;
MODULE TIMER64_0;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_0.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER0_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_0.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER0_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_0.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER0_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_0.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER0_CFG.memtr_dbg_write_opin;
END TIMER64_0;
MODULE TIMER64_1;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_1.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER1_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_1.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER1_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_1.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER1_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_1.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER1_CFG.memtr_dbg_write_opin;
END TIMER64_1;
MODULE TIMER64_2;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_2.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER2_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_2.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER2_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_2.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER2_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_2.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER2_CFG.memtr_dbg_write_opin;
END TIMER64_2;
MODULE TIMER64_3;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_3.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER3_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_3.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER3_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_3.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER3_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_3.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER3_CFG.memtr_dbg_write_opin;
END TIMER64_3;
MODULE TIMER64_4;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_4.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER4_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_4.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER4_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_4.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER4_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_4.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER4_CFG.memtr_dbg_write_opin;
END TIMER64_4;
MODULE TIMER64_5;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_5.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER5_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_5.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER5_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_5.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER5_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_5.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER5_CFG.memtr_dbg_write_opin;
END TIMER64_5;
MODULE TIMER64_6;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_6.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER6_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_6.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER6_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_6.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER6_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_6.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER6_CFG.memtr_dbg_write_opin;
END TIMER64_6;
MODULE TIMER64_7;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.TIMER64_7.mt_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER7_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.TIMER64_7.mt_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER7_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.TIMER64_7.mt_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER7_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.TIMER64_7.mt_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.TIMER7_CFG.memtr_dbg_write_opin;
END TIMER64_7;
MODULE EDMA;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/sim_edma.so;
//! "C" interfaces to the DLL
INIT_FUNC dma_init_func;
INIT_DONE_FUNC dma_init_done_func;
CONNECT_FUNC dma_connect_func;
QUIT_FUNC dma_quit_func;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE SHARED;
//*********************************//
//! EDMA v3 Architecture Entries !//
//*********************************//
CLOCK_DIVIDE_RATIO 3;
NUM_DMA_CHANNELS 64;
NUM_QDMA_CHANNELS 8;
NUM_INT_CHANNELS 64;
NUM_PARAM_ENTRIES 512;
NUM_EVENT_QUEUES 4;
NUM_TCS 4;
CHANNEL_MAP_EXISTS YES;
NUM_REGIONS 8;
EXPOSE_MEMTR_PER_TC YES;
TC0_MSTID 29;
TC1_MSTID 31;
TC2_MSTID 33;
TC3_MSTID 35;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.EDMA.tpcc_reg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_CC.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.EDMA.tpcc_reg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_CC.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.EDMA.tpcc_reg_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_CC.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.EDMA.tpcc_reg_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_CC.memtr_dbg_write_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC0.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC0_M.memtr_read_ipin;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC0.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC0_M.memtr_write_ipin;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC0.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC0_M.memtr_dbg_read_ipin;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC0.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC0_M.memtr_dbg_write_ipin;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC1.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC1_M.memtr_read_ipin;
CONNECT10 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC1.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC1_M.memtr_write_ipin;
CONNECT11 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC1.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC1_M.memtr_dbg_read_ipin;
CONNECT12 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC1.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC1_M.memtr_dbg_write_ipin;
CONNECT13 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC2.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC2_M.memtr_read_ipin;
CONNECT14 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC2.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC2_M.memtr_write_ipin;
CONNECT15 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC2.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC2_M.memtr_dbg_read_ipin;
CONNECT16 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC2.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC2_M.memtr_dbg_write_ipin;
CONNECT17 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC3.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC3_M.memtr_read_ipin;
CONNECT18 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC3.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC3_M.memtr_write_ipin;
CONNECT19 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC3.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC3_M.memtr_dbg_read_ipin;
CONNECT20 System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC3.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC3_M.memtr_dbg_write_ipin;
BUSCONNECT1 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC0. , System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC0_S.;
BUSCONNECT2 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC1. , System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC1_S.;
BUSCONNECT3 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC2. , System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC2_S.;
BUSCONNECT4 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.EDMA.3PTC3. , System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.EDMA_TC3_S.;
END EDMA;
MODULE CP_INTC0;
//! Module Name.
NAME CP_INTC0;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 208;
NUMBER_OF_CHANNELS 56; //For GAUSS
NUMBER_OF_HOST_INTERRUPT 56;//For GAUSS
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
HOST_CHANNEL_MAP29 29;
HOST_CHANNEL_MAP30 30;
HOST_CHANNEL_MAP31 31;
HOST_CHANNEL_MAP32 32;
HOST_CHANNEL_MAP33 33;
HOST_CHANNEL_MAP34 34;
HOST_CHANNEL_MAP35 35;
HOST_CHANNEL_MAP36 36;
HOST_CHANNEL_MAP37 37;
HOST_CHANNEL_MAP38 38;
HOST_CHANNEL_MAP39 39;
HOST_CHANNEL_MAP40 40;
HOST_CHANNEL_MAP41 41;
HOST_CHANNEL_MAP42 42;
HOST_CHANNEL_MAP43 43;
HOST_CHANNEL_MAP44 44;
HOST_CHANNEL_MAP45 45;
HOST_CHANNEL_MAP46 46;
HOST_CHANNEL_MAP47 47;
HOST_CHANNEL_MAP48 48;
HOST_CHANNEL_MAP49 49;
HOST_CHANNEL_MAP50 50;
HOST_CHANNEL_MAP51 51;
HOST_CHANNEL_MAP52 52;
HOST_CHANNEL_MAP53 53;
HOST_CHANNEL_MAP54 54;
HOST_CHANNEL_MAP55 55;
END CP_INTC0;
MODULE CP_INTC1;
//! Module Name.
NAME CP_INTC1;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 160; //<CHECK>
NUMBER_OF_CHANNELS 29; //For GAUSS
NUMBER_OF_HOST_INTERRUPT 29; //For GAUSS
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
END CP_INTC1;
MODULE CP_INTC2;
//! Module Name.
NAME CP_INTC2;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 72; //<CHECK>
NUMBER_OF_CHANNELS 40; //For GAUSS
NUMBER_OF_HOST_INTERRUPT 40; //For GAUSS
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
HOST_CHANNEL_MAP29 29;
HOST_CHANNEL_MAP30 30;
HOST_CHANNEL_MAP31 31;
HOST_CHANNEL_MAP32 32;
HOST_CHANNEL_MAP33 33;
HOST_CHANNEL_MAP34 34;
HOST_CHANNEL_MAP35 35;
HOST_CHANNEL_MAP36 36;
HOST_CHANNEL_MAP37 37;
HOST_CHANNEL_MAP38 38;
HOST_CHANNEL_MAP39 39;
END CP_INTC2;
MODULE VCP2_0;
TYPE SHARED;
SSI_VER SSI_1.1;
NAME VCP2_0;//Has to be unique
DLL ../../../bin/components/tisim_civ_vcp_ca.so;
INIT_FUNC init_vcp_model;
INIT_DONE_FUNC vcp_init_done;
QUIT_FUNC vcp_quit;
MODULE INTERFACES;
//NOTE: don't change the names of the VCP interfaces, they are fixed
CONNECT1 System.C66XX_N.SHARED_SYSTEM.VCP2_0.CPU_CFG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.VCP2_0.CPU_CFG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.VCP2_0.CPU_DBG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.VCP2_0.CPU_DBG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_CFG.memtr_dbg_write_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.VCP2_0.DMA_CFG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_SLV.memtr_read_opin;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.VCP2_0.DMA_CFG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_SLV.memtr_write_opin;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.VCP2_0.DMA_DBG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_SLV.memtr_dbg_read_opin;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.VCP2_0.DMA_DBG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_0_SLV.memtr_dbg_write_opin;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_CLK, System.C66XX_N.SHARED_SYSTEM_INTF.clock_out;
CONNECT10 System.C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_RESET, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT11 System.C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_ENDIAN, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 VCP_DMA_START_ADDRESS , 0x22A00000;
INPUT2 VCP_DMA_END_ADDRESS , 0x22A0FFFF;
INPUT3 VCP_CFG_START_ADDRESS, 0x021D0000;
INPUT4 VCP_CFG_END_ADDRESS, 0x021D00FF;
INPUT5 PID, 0x480A0000;
END USER_INPUTS;
END VCP2_0;
MODULE VCP2_1;
TYPE SHARED;
SSI_VER SSI_1.1;
NAME VCP2_1;//Has to be unique
DLL ../../../bin/components/tisim_civ_vcp_ca.so;
INIT_FUNC init_vcp_model;
INIT_DONE_FUNC vcp_init_done;
QUIT_FUNC vcp_quit;
MODULE INTERFACES;
//NOTE: don't change the names of the VCP interfaces, they are fixed
CONNECT1 System.C66XX_N.SHARED_SYSTEM.VCP2_1.CPU_CFG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_CFG.memtr_read_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.VCP2_1.CPU_CFG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_CFG.memtr_write_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.VCP2_1.CPU_DBG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.VCP2_1.CPU_DBG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_CFG.memtr_dbg_write_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.VCP2_1.DMA_CFG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_SLV.memtr_read_opin;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.VCP2_1.DMA_CFG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_SLV.memtr_write_opin;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.VCP2_1.DMA_DBG_RD, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_SLV.memtr_dbg_read_opin;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.VCP2_1.DMA_DBG_WR, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.VCP2_1_SLV.memtr_dbg_write_opin;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_CLK, System.C66XX_N.SHARED_SYSTEM_INTF.clock_out;
CONNECT10 System.C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_RESET, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT11 System.C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_ENDIAN, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 VCP_DMA_START_ADDRESS , 0x22B00000;
INPUT2 VCP_DMA_END_ADDRESS , 0x22B0FFFF;
INPUT3 VCP_CFG_START_ADDRESS, 0x021D4000;
INPUT4 VCP_CFG_END_ADDRESS, 0x021D40FF;
INPUT5 PID, 0x480A0000;
END USER_INPUTS;
END VCP2_1;
MODULE SEMAPHORE;
TYPE SHARED;
SSI_VER SSI_1.1;
NAME semaphore2;
DLL ../../../bin/components/semaphore2.so;
INIT_FUNC semaphore2_init;
INIT_DONE_FUNC semaphore2_init_done;
QUIT_FUNC semaphore2_quit;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 PID, 0x48021200;
INPUT3 NUM_MASTERS, 4; //Same as TCI6616
INPUT4 NUM_RESOURCES, 32;
END USER_INPUTS;
END SEMAPHORE;
MODULE TCP3D_A;
TYPE SHARED;
SSI_VER SSI_1.1;
NAME tcp3d_a;
DLL ../../../bin/components/tcp3d.so;
INIT_FUNC tcp3d_init;
INIT_DONE_FUNC tcp3d_init_done;
QUIT_FUNC tcp3d_quit;
MODULE USER_INPUTS;
INPUT1 PID , 0x4804011E;
INPUT2 CPU_NAME , SHARED;
INPUT3 CLK_DIV , 0x2;
//INPUT4 DBG_LOG , C:\Tcp3d_a_Debug.log;
END USER_INPUTS;
END TCP3D_A;
MODULE IPC;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_inter_core_interrupt.so;
INIT_FUNC inter_core_interrupt_init_func;
INIT_DONE_FUNC inter_core_interrupt_init_done_func;
QUIT_FUNC inter_core_interrupt_quit_func;
CLOCK_DIVIDE_RATIO 6; //<CHECK>
NO_OF_CORES 2;
WAITING_TIME_WINDOW 8; //<CHECK>
NMIGR_SUPPORT ON; //Enabling NMIGR support
NMIGR_START_OFFSET 0; //Indicates the offset from the start of the Inter-core memory region for inter-core NMIGR
NMI_PULSE_WINDOW 1;
IPCGR_START_OFFSET 16; //offset in no. of bytes, offset/4
IPCAR_START_OFFSET 32; //offset in no. of bytes, offset/4
ENABLE_WARNING_MSGS OFF;
HOSTREG_OFFSET_FROM_IPCREG_START 15;
END IPC;
MODULE GPIO;
NAME gpio;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_gpio_pv.so;
INIT_FUNC gpio_init;
INIT_DONE_FUNC gpio_init_done;
QUIT_FUNC gpio_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_cfg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.GPIO_CFG.memtr_write_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_cfg_read_ipin,System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.GPIO_CFG.memtr_read_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.GPIO_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.GPIO_CFG.memtr_dbg_write_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_reset_ipin, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_endian_ipin, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_error_opin,System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.GPIO.gpio_error_opin,System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 NUM_GPINT_PINS, 32; //Gauss supports 32
INPUT3 PID, 0x44831105;
END USER_INPUTS;
END GPIO;
//Same as TCI6616 for GAUSS
MODULE QUEUE_MANAGER;
NAME queue_manager;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/qmss.so;
//CPU_VIEW <<CPU_MODULE_NAME>>; //Update this entry with the CPU module name in the system
INIT_FUNC qmss_init;
INIT_DONE_FUNC qmss_init_done;
QUIT_FUNC qmss_quit;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME , SHARED;
//START:Darshan
INPUT2 NUM_QM , 1;
INPUT3 QUEUES_PER_QM , 8192;
INPUT4 MEM_REGN_PER_QM , 20;
INPUT5 NUM_PDSP , 2;
INPUT6 NUM_INTD , 1;
INPUT7 NUM_TIMER , 2;
INPUT8 NUM_MCDMA , 1;
INPUT9 LINKRAM_BASE , 0x00080000;
INPUT10 LINKRAM_INDEXES , 16384;
INPUT11 QM_CFG_BASE , 0x00068000;
INPUT12 QM_CFG_OFFSET , 0x00002000;
INPUT13 QM_DESC_BASE , 0x0006a000;
INPUT14 QM_DESC_OFFSET , 0x00002000;
INPUT15 QM_QUE_BASE , 0x00020000;
INPUT16 QM_QUE_OFFSET , 0x00020000;
INPUT17 QM_PEEK_BASE , 0x00000000;
INPUT18 QM_PEEK_OFFSET , 0x00020000;
INPUT19 QM_STATUS_BASE , 0x00062000;
INPUT20 QM_STATUS_OFFSET , 0x00000400;
INPUT21 QM_PROXY_BASE , 0x00040000;
INPUT22 QM_PROXY_OFFSET , 0x00020000;
INPUT23 PDSP_GBL_SCRTCH_BASE , 0x00000000; //na on Ny/Sh/Tn/Aptn
INPUT24 PDSP_GBL_SCRTCH_SIZE , 0x00000000; //na on Ny/Sh/Tn/Aptn
INPUT25 PDSP_LCL_SCRTCH_BASE , 0x000b8000;
INPUT26 PDSP_LCL_SCRTCH_OFFSET, 0x00004000;
INPUT27 PDSP_REG_BASE , 0x0006E000;
INPUT28 PDSP_REG_OFFSET , 0x00001000;
INPUT29 PDSP_DBG_BASE , 0x000b0000;
INPUT30 PDSP_DBG_OFFSET , 0x00001000;
INPUT31 PDSP_IRAM_BASE , 0x00060000;
INPUT32 PDSP_IRAM_OFFSET , 0x00001000;
INPUT33 PDSP_SCRTCH_EVEN_SIZE , 0x00004000;
INPUT34 PDSP_SCRTCH_ODD_SIZE , 0x00002000;
INPUT35 QM_INTD_BASE , 0x000a0000;
INPUT36 QM_INTD_OFFSET , 0x00001000;
INPUT37 QM_TIMER_BASE , 0x000a8000;
INPUT38 QM_TIMER_OFFSET , 0x00000800;
INPUT39 QM_MCDMA_BASE , 0x00090000;
INPUT40 QM_MCDMA_OFFSET , 0x00000800;
INPUT41 TOTAL_CFG_SPACE , 0x000c0000;
INPUT42 INTC_1ST_QNUM , 650;
INPUT43 INTC_NUM_QUEUES , 22;
INPUT44 STARVATION_1ST_QNUM , 736;
INPUT45 STARVATION_NUM_QUEUES , 64;
INPUT46 TIMER_TICK , 7;
INPUT47 TIMER_RESOLUTION , 1000;
INPUT48 NUM_PKTDMA , 2; //Num pktDMA defs to follow
INPUT49 PKTDMA_1_TXQ , 800; //Infra1
INPUT50 PKTDMA_1_NUMQ , 32;
INPUT51 PKTDMA_2_TXQ , 672; //SRIO
INPUT52 PKTDMA_2_NUMQ , 16;
// INPUT53 DEBUG_LOG , qmss_debug_log.txt;
//END:Darshan
END USER_INPUTS;
END QUEUE_MANAGER;
MODULE CDMA_INFRA;
NAME cdma_qm;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/cdma.so;
//CPU_VIEW <<CPU_MODULE_NAME>>; //Update this entry with the CPU module name in the system
INIT_FUNC cdma_init;
INIT_DONE_FUNC cdma_init_done;
QUIT_FUNC cdma_quit;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME , SHARED;
INPUT2 NUM_RX_CHANNELS , 32;
INPUT3 NUM_TX_CHANNELS , 32;
INPUT4 NUM_RX_FLOWS , 64;
INPUT5 RX_FIFO_SIZE , 32;
INPUT6 TX_FIFO_SIZE , 33; //(+1 for CDMA) as per Dave's mail
INPUT7 FIFO_DESC_SIZE , 8;
INPUT8 RX_FIFO_DEPTH , 32;
INPUT9 TX_FIFO_DEPTH , 48;
INPUT10 TX_CHUNK_READ , 128;
INPUT11 GLOBAL_CFG_OFFSET, 0x0006c000;
INPUT12 TX_CHAN_CFG_OFFSET, 0x0006c400;
INPUT13 RX_CHAN_CFG_OFFSET, 0x0006c800;
INPUT14 TX_SCHED_CFG_OFFSET, 0x0006cc00;
INPUT15 RX_FLOW_CFG_OFFSET, 0x0006d000;
INPUT16 QM_QUE_MMR_BASE , 0x34020000; //As per Dave's mail
//Start:Darshan
INPUT17 FIRST_HW_QNUM , 800;
INPUT18 PACKET_OFFSET , 0;
INPUT19 PACKET_TAG , 0;
INPUT20 TX_SCHED_BYPASS , 0;
INPUT21 TX_DESCRIPTOR_RELEASE , 0;
INPUT22 LOOPBACK_MODE , 1;
INPUT23 PAYLOAD_TRANSPARENCY , 1;
INPUT24 CYCLE_APPROX_MODE, 0;
INPUT25 QM_POP_DELAY, 30;
INPUT26 QM_PUSH_DELAY, 45;
INPUT27 MEM_RW_DELAY, 1;
INPUT28 CLK_DIV, 3;
// INPUT29 DEBUG_LOG, CDMA_qmss_debug_log.txt;
//End:Darshan
END USER_INPUTS;
END CDMA_INFRA;
MODULE INTD_TCP3D_A;
NAME intd_tcp3d_a;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_combiner_intd.so;
INIT_FUNC init_combiner_intd;
INIT_DONE_FUNC init_combiner_intd_done;
QUIT_FUNC quit_combiner_intd;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME , SHARED;
INPUT2 NUMBER_OF_INTERRUPTS , 2;
END USER_INPUTS;
END INTD_TCP3D_A;
MODULE PCIE;
NAME pciess;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_pciess.so;
INIT_FUNC pciess_init;
INIT_DONE_FUNC pciess_init_done;
QUIT_FUNC pciess_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.PCIE.pciess_reset, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.PCIE.pciess_big_endian_ipin, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.PCIE.pciess_slv_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PCIE_SLV.memtr_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.PCIE.pciess_slv_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PCIE_SLV.memtr_write_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.PCIE.pciess_slv_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PCIE_SLV.memtr_dbg_read_opin;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.PCIE.pciess_slv_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PCIE_SLV.memtr_dbg_write_opin;
//NOTE:
// Master interface not modeled.
// Interrupt functionality not modeled, dll not connected.
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 PID , 0x4e300000;
INPUT2 CLK_DIV , 3;
INPUT3 CFG_TYPE, 0;
INPUT4 CPU_NAME, SHARED;
INPUT5 CFG_BASE, 0x21800000;
END USER_INPUTS;
END PCIE;
MODULE MEMTR_MSMC_Adaptor;
NAME memtr_msmc_adaptor;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_MSMC_Adaptor;
MODULE MEMTR_FLATMEM_36BIT_Adaptor;
NAME memtr_flatmem_36bit_adaptor;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_FLATMEM_36BIT_Adaptor;
MODULE MEMTR_CGEM0_Slv_Adaptor;
NAME memtr_cgem0_slv_adaptor;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_CGEM0_Slv_Adaptor;
MODULE MEMTR_CGEM1_Slv_Adaptor;
NAME memtr_cgem1_slv_adaptor;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_CGEM1_Slv_Adaptor;
MODULE FLATMEM_36BIT;
NAME flatmem_36bit; // Same name as MODULE
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memstore_36bit_ssi.so;
INIT_FUNC memstore_36bit_init;
INIT_DONE_FUNC memstore_36bit_init_done;
QUIT_FUNC memstore_36bit_quit;
END FLATMEM_36BIT;
MODULE PSC;
NAME psc;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_aptn_psc_ssi.so;
INIT_FUNC init_aptn_psc_intf;
INIT_DONE_FUNC init_done_aptn_psc_intf;
QUIT_FUNC quit_aptn_psc_intf;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.PSC.mbus_in_write, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PSC_CFG.memtr_write_opin;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.PSC.mbus_in_read, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PSC_CFG.memtr_read_opin;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.PSC.mbus_in_dbg_read, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PSC_CFG.memtr_dbg_read_opin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.PSC.mbus_in_dbg_write, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.PSC_CFG.memtr_dbg_write_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.PSC.rst_in, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.PSC.endian_in, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.PSC.errmsg, System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.PSC.errmsg, System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 CPU_NAME,SHARED;
INPUT2 PID, 0x44825A00;
INPUT3 NUM_POWER_DOMAINS, 32;
//Power domain assignments for modules
//As per GAUSS power spec
INPUT4 MDCFG0_PWRDOM, 0;
INPUT5 MDCFG1_PWRDOM, 0;
INPUT6 MDCFG2_PWRDOM, 0;
INPUT7 MDCFG3_PWRDOM, 0;
INPUT8 MDCFG4_PWRDOM, 0;
INPUT9 MDCFG5_PWRDOM, 1;
INPUT10 MDCFG6_PWRDOM, 1;
INPUT11 MDCFG7_PWRDOM, 2;
INPUT12 MDCFG8_PWRDOM, 2;
INPUT13 MDCFG9_PWRDOM, 2;
INPUT14 MDCFG10_PWRDOM, 3;
INPUT15 MDCFG11_PWRDOM, 4;
INPUT16 MDCFG12_PWRDOM, 5;
INPUT17 MDCFG13_PWRDOM, 6;
INPUT18 MDCFG14_PWRDOM, 7;
INPUT19 MDCFG15_PWRDOM, 8;
INPUT20 MDCFG16_PWRDOM, 8;
INPUT21 MDCFG17_PWRDOM, 9;
INPUT22 MDCFG18_PWRDOM, 10;
INPUT23 MDCFG19_PWRDOM, 11;
INPUT24 MDCFG20_PWRDOM, 12;
INPUT25 MDCFG21_PWRDOM, 12;
INPUT26 MDCFG22_PWRDOM, 12;
INPUT27 MDCFG23_PWRDOM, 13;
INPUT28 MDCFG24_PWRDOM, 14;
INPUT29 MDCFG25_PWRDOM, 14;
INPUT30 MDCFG26_PWRDOM, 15;
INPUT31 MDCFG27_PWRDOM, 15;
INPUT32 MDCFG28_PWRDOM, 16;
INPUT33 MDCFG29_PWRDOM, 17;
INPUT34 MDCFG30_PWRDOM, 18;
INPUT35 MDCFG31_PWRDOM, 0;
END USER_INPUTS;
END PSC;
MODULE SSI2SOCK_PORT0;
NAME ssi2sock;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/ssi2sock.so;
INIT_FUNC ssi2sock_init;
INIT_DONE_FUNC ssi2sock_init_done;
QUIT_FUNC ssi2sock_quit;
MODULE INTERFACES;
//SSI connections to CPU and other peripheral;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_reset, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_receive_data, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_opin_port0;
CONNECT3 System.C66XX_N.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_send_data, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ipin_port0;
// Propogate the error to every CPU model.
CONNECT4 System.C66XX_N.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_error_opin, System.C66XX_N.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_error_opin, System.C66XX_N.CPU_SYSTEM_1.CPU1.error_intf_ssi;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 SOCK, OFF;
INPUT2 SOCK_PORT, 2048;
INPUT3 MAX_NUM_BYTES_PER_SOCK_RECV, 16560; // Number of bytes attempted to receive
// for every Socket receive call
// Assuming each SRIO packet contains 4140
// bytes (max), the simulator is configured to
// handle upto 4 SRIO packets, in one socket
// read call.
INPUT4 RECV_FIFO_LENGTH, 10; // Fifo length. Each fifo entry can
// hold MAX_NUM_BYTES_PER_SOCK_RECV bytes
INPUT5 CPU_NAME, SHARED;
INPUT6 SOCK_PROTOCOL, TCP;
INPUT7 SOCK_TYPE, SERVER;
END USER_INPUTS;
END SSI2SOCK_PORT0;
MODULE SRIO;
NAME srio;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_srio.so;
INIT_FUNC srio_init;
INIT_DONE_FUNC srio_init_done;
QUIT_FUNC srio_quit;
MODULE INTERFACES;
//! NOTE: SRIO Master( Master port for all other traffic other than CPPI) has not been integrated)
CONNECT1 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_reset, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_big_endian_ipin, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian;
//These pins setup the Streaming interfaces
CONNECT3 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tstrm_thread_mready_opin, System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_thread_mready_ipin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tstrm_thread_sready_ipin, System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_thread_sready_opin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tstrm_data_opin, System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_data_ipin;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tstrm_data_accept_ipin, System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_data_accept_opin;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_thread_mready_opin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rstrm_thread_mready_ipin;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_thread_sready_ipin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rstrm_thread_sready_opin;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_data_opin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rstrm_data_ipin;
CONNECT10 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_data_accept_ipin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rstrm_data_accept_opin;
// CFG and DBG read/write pins
CONNECT11 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_cfg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_CFG.memtr_read_opin;
CONNECT12 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_cfg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_CFG.memtr_write_opin;
CONNECT13 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_cfg_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_CFG.memtr_dbg_read_opin;
CONNECT14 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_cfg_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_CFG.memtr_dbg_write_opin;
// Data region interface
CONNECT15 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_DMA.memtr_read_opin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_dma_read_ipin;
CONNECT16 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_DMA.memtr_write_opin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_dma_write_ipin;
CONNECT17 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_DMA.memtr_dbg_read_opin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_dma_dbg_read_ipin;
CONNECT18 System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.SRIO_DMA.memtr_dbg_write_opin, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_dma_dbg_write_ipin;
// Connect SRIO output ports and ready pins to inputs to loopback for testing
//CONNECT19 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_opin_port0, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ipin_port0;
CONNECT19 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_opin_port1, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ipin_port1;
CONNECT20 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_opin_port2, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ipin_port2;
CONNECT21 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_opin_port3, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ipin_port3;
//CONNECT23 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port0, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port0;
CONNECT22 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port1, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port1;
CONNECT23 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port2, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port2;
CONNECT24 System.C66XX_N.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port3, System.C66XX_N.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port3;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 CLK_DIV, 3;
// INPUT3 FILE_LOG, srio_dbg;
END USER_INPUTS;
END SRIO;
////////////////////////////////////////////////////////////////////////////////////////////////////
////////// Config spec for CDMA_SRIO Module ////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
MODULE CDMA_SRIO;
NAME cdma_srio;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/cdma.so;
INIT_FUNC cdma_init;
INIT_DONE_FUNC cdma_init_done;
QUIT_FUNC cdma_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_reset_ipin, System.C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_endian_ipin, System.C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian;
//These pins allow the CDMA to read/write memory.
CONNECT3 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_mstr_read_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_SRIO_MASTER.memtr_read_ipin;
CONNECT4 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_mstr_write_opin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_SRIO_MASTER.memtr_write_ipin;
CONNECT5 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_cfg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_SRIO_CFG.memtr_read_opin;
CONNECT6 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_cfg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_SRIO_CFG.memtr_write_opin;
CONNECT7 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_dbg_read_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_SRIO_CFG.memtr_dbg_read_opin;
CONNECT8 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_dbg_write_ipin, System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_SRIO_CFG.memtr_dbg_write_opin;
CONNECT9 System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_rx_teardown_req_opin, System.C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_rx_teardown_ack_ipin;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 NUM_RX_CHANNELS, 16;
INPUT3 NUM_TX_CHANNELS, 16;
INPUT4 NUM_RX_FLOWS, 20;
INPUT5 RX_FIFO_SIZE, 1024;
INPUT6 TX_FIFO_SIZE, 1025; // +1 is for CDMA internal usage
INPUT7 FIFO_DESC_SIZE, 8;
INPUT8 RX_FIFO_DEPTH, 16;
INPUT9 TX_FIFO_DEPTH, 16;
INPUT10 TX_CHUNK_READ, 1024;
INPUT11 GLOBAL_CFG_OFFSET, 0x00001000;
INPUT12 TX_CHAN_CFG_OFFSET, 0x00001400;
INPUT13 RX_CHAN_CFG_OFFSET, 0x00001800;
INPUT14 TX_SCHED_CFG_OFFSET,0x00001c00;
INPUT15 RX_FLOW_CFG_OFFSET, 0x00002000;
INPUT16 QM_QUE_MMR_BASE, 0x34020000; //<<CHECK>>
//Start:Darshan
INPUT17 FIRST_HW_QNUM, 672;
INPUT18 PACKET_OFFSET, 1;
INPUT19 PACKET_TAG, 0;
INPUT20 TX_SCHED_BYPASS, 0;
INPUT21 TX_DESCRIPTOR_RELEASE, 1;
INPUT22 LOOPBACK_MODE, 0;
INPUT23 PAYLOAD_TRANSPARENCY, 0;
INPUT24 CYCLE_APPROX_MODE, 0;
INPUT25 QM_POP_DELAY, 30;
INPUT26 QM_PUSH_DELAY, 45;
INPUT27 MEM_RW_DELAY, 1;
INPUT28 CLK_DIV, 3;
//INPUT29 DEBUG_LOG , C:\CDMA_srio_Debug.log;
//End:Darshan
END USER_INPUTS;
END CDMA_SRIO;
END SHARED_SYSTEM;
END C66XX_N;
// CONNECTIONS
// CGEM program path for other
CONNECT1 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_prog_mif, C66XX_N.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT2 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_prog_mif, C66XX_N.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
// L1D and L1P connection for CGEM program path
CONNECT3 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x10E00000, 0x10E07FFF, 0;
CONNECT4 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x11E00000, 0x11E07FFF, 0;
CONNECT5 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x10F00000, 0x10F07FFF, 0;
CONNECT6 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x11F00000, 0x11F07FFF, 0;
//CGEM_SSI connections to CPU mem_map
CONNECT7 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_data_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT8 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_data_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0, 0xFFFFFFFF, 0;
// L1D and L1P connection for CGEM Data path
CONNECT9 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0x10E00000, 0x10E07FFF, 0;
CONNECT10 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0x11E00000, 0x11E07FFF, 0;
CONNECT11 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0x10F00000, 0x10F07FFF, 0;
CONNECT12 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0x11F00000, 0x11F07FFF, 0;
// Register for CGEM and XMC mapping
CONNECT13 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_reg_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT14 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_reg_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0x01800000, 0x01BFFFFF, 0;
//CGEM INTSEL Connections with CPU mem_map
CONNECT15 C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT16 C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
//! Connections of IDMA with CPU
CONNECT17 C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT18 C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
// Register for XMC mapping
CONNECT19 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_reg_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT20 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_reg_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0x08000000, 0x0800FFFF, 0;
//! Connections of IDMA with CGEM_SSI
CONNECT21 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.idma_mem_map, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT22 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.idma_mem_map, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
// L1D and L1P connection forIDMA
CONNECT23 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT24 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT25 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT26 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
//MSMC connections with CGEM SSI
CONNECT27 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_read_input_ipin, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_read_output_opin;
CONNECT28 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_write_input_ipin, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_write_output_opin;
CONNECT29 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_dbg_read_input_ipin, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_dbg_read_output_opin;
CONNECT30 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_dbg_write_input_ipin, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_dbg_write_output_opin;
CONNECT31 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_read_input_ipin, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_read_output_opin;
CONNECT32 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_write_input_ipin, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_write_output_opin;
CONNECT33 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_dbg_read_input_ipin, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_dbg_read_output_opin;
CONNECT34 C66XX_N.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_dbg_write_input_ipin, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_dbg_write_output_opin;
//SEMAPHORE connections with MEMTRs
CONNECT35 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SEMAPHORE2_CFG.memtr_read_opin, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_cfg_read_ipin;
CONNECT36 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SEMAPHORE2_CFG.memtr_write_opin, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_cfg_write_ipin;
CONNECT37 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SEMAPHORE2_CFG.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_dbg_read_ipin;
CONNECT38 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SEMAPHORE2_CFG.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_dbg_write_ipin;
//Driving CMD_ID and PRIV_ID through MSMC adaptor
//VBUSM CMD packet
CONNECT39 C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_vbusm_cmd_output_opin;
CONNECT40 C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_vbusm_cmd_output_opin;
//TCP3D_A connections with MEMTRs
//TCP3D_A Config
CONNECT41 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_CFG.memtr_read_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_cfg_read_ipin;
CONNECT42 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_CFG.memtr_write_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_cfg_write_ipin;
CONNECT43 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_CFG.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_cfg_dbg_read_ipin;
CONNECT44 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_CFG.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_cfg_dbg_write_ipin;
//TCP3D_A Slave
CONNECT45 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_SLV.memtr_read_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_dma_read_ipin;
CONNECT46 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_SLV.memtr_write_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_dma_write_ipin;
CONNECT47 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_SLV.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_dma_dbg_read_ipin;
CONNECT48 C66XX_N.SHARED_SYSTEM.INTERCONNECT.TCP3D_A_SLV.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_dma_dbg_write_ipin;
//QM connections with MEMTRs
//QM Config
CONNECT49 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_CFG.memtr_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_cfg_read_ipin;
CONNECT50 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_CFG.memtr_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_cfg_write_ipin;
CONNECT51 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_CFG.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dbg_read_ipin;
CONNECT52 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_CFG.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dbg_write_ipin;
//QM Low Accumulator
CONNECT53 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_PDSP_COMMAND_CFG.memtr_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_read_ipin;
CONNECT54 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_PDSP_COMMAND_CFG.memtr_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_write_ipin;
CONNECT55 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_PDSP_COMMAND_CFG.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_dbg_read_ipin;
CONNECT56 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_PDSP_COMMAND_CFG.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_dbg_write_ipin;
//QM High Accumulator
//CONNECT57 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_HI_ACC_CFG.memtr_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_hi_acc_cmd_read_ipin;
//CONNECT58 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_HI_ACC_CFG.memtr_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_hi_acc_cmd_write_ipin;
//CONNECT59 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_HI_ACC_CFG.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_hi_acc_cmd_dbg_read_ipin;
//CONNECT60 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_HI_ACC_CFG.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_hi_acc_cmd_dbg_write_ipin;
//QM Master Accumulator
CONNECT57 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_PDSP_MASTER.memtr_read_ipin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_master_read_opin;
CONNECT58 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_PDSP_MASTER.memtr_write_ipin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_master_write_opin;
//CDMA_INFRA connections with MEMTRs
//CDMA_INFRA Config
CONNECT59 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_INFRA_CFG.memtr_read_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_cfg_read_ipin;
CONNECT60 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_INFRA_CFG.memtr_write_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_cfg_write_ipin;
CONNECT61 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_INFRA_CFG.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_dbg_read_ipin;
CONNECT62 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_INFRA_CFG.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_dbg_write_ipin;
//CDMA_INFRA Master
CONNECT63 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_INFRA_MASTER.memtr_read_ipin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_mstr_read_opin;
CONNECT64 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CDMA_INFRA_MASTER.memtr_write_ipin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_mstr_write_opin;
//FLATMEM_36BIT connections with MSMC
CONNECT65 C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_read_input_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_read_output_opin;
CONNECT66 C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_write_input_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_write_output_opin;
CONNECT67 C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_dbg_read_input_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_dbg_read_output_opin;
CONNECT68 C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_dbg_write_input_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_dbg_write_output_opin;
//CONNECT151 C66XX_N.SHARED_SYSTEM.INTERCONNECT2.MSMC_DDREMIF_MASTER.memtr_read_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_read_output_opin;
//CONNECT152 C66XX_N.SHARED_SYSTEM.INTERCONNECT2.MSMC_DDREMIF_MASTER.memtr_write_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_write_output_opin;
//CONNECT153 C66XX_N.SHARED_SYSTEM.INTERCONNECT2.MSMC_DDREMIF_MASTER.memtr_dbg_read_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_dbg_read_output_opin;
//CONNECT154 C66XX_N.SHARED_SYSTEM.INTERCONNECT2.MSMC_DDREMIF_MASTER.memtr_dbg_write_ipin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_dbg_write_output_opin;
//MEMTR connections to SMS and SES interfaces of MSMC
//SMS connections
CONNECT69 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SMS_SLV.memtr_read_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_read_input_ipin;
CONNECT70 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SMS_SLV.memtr_write_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_write_input_ipin;
CONNECT71 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SMS_SLV.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_dbg_read_input_ipin;
CONNECT72 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SMS_SLV.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_dbg_write_input_ipin;
//SES connections
CONNECT73 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SES_SLV.memtr_read_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SES_memtr_read_input_ipin;
CONNECT74 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SES_SLV.memtr_write_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SES_memtr_write_input_ipin;
CONNECT75 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SES_SLV.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SES_memtr_dbg_read_input_ipin;
CONNECT76 C66XX_N.SHARED_SYSTEM.INTERCONNECT.SES_SLV.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.MSMC.msmc_SES_memtr_dbg_write_input_ipin;
//RESET Connections
CONNECT77 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_reset_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_RESET;
CONNECT78 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_reset_ipin, C66XX_N.CPU_SYSTEM_1.CPU1_RESET;
CONNECT79 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM_INTF.reset_in;
CONNECT80 C66XX_N.SHARED_SYSTEM.MSMC.msmc_reset_ipin, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT81 C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_reset_ipin, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT82 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_0.reset;
CONNECT83 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_1.reset;
CONNECT84 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_2.reset;
CONNECT85 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_3.reset;
CONNECT86 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_4.reset;
CONNECT87 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_5.reset;
CONNECT88 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_6.reset;
CONNECT89 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.TIMER64_7.reset;
CONNECT90 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.EDMA.reset;
CONNECT91 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_reset_in, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT92 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_reset_in, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT93 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_reset_in, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT94 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_reset_in, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT95 C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_reset_ipin, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT96 C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_reset_ipin, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT97 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_reset_ipin, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT98 C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_reset_ipin, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
CONNECT99 System.SimBridge.global_reset_list, C66XX_N.SHARED_SYSTEM.IPC.reset;
//Endianess Connections
CONNECT100 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT101 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_endian_ipin, C66XX_N.CPU_SYSTEM_1.CPU1_endianness;
//! since the whole system is of the same endianness, connecting any CPU's endian to the entire shared Components
CONNECT102 C66XX_N.SHARED_SYSTEM.MSMC.msmc_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT103 C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT104 C66XX_N.SHARED_SYSTEM.TIMER64_0.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT105 C66XX_N.SHARED_SYSTEM.TIMER64_1.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT106 C66XX_N.SHARED_SYSTEM.TIMER64_2.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT107 C66XX_N.SHARED_SYSTEM.TIMER64_3.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT108 C66XX_N.SHARED_SYSTEM.TIMER64_4.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT109 C66XX_N.SHARED_SYSTEM.TIMER64_5.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT110 C66XX_N.SHARED_SYSTEM.TIMER64_6.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT111 C66XX_N.SHARED_SYSTEM.TIMER64_7.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT112 C66XX_N.CPU_SYSTEM_0.CPU0_endianness, C66XX_N.SHARED_SYSTEM.EDMA.endian_in;
CONNECT113 C66XX_N.CPU_SYSTEM_0.CPU0_endianness, C66XX_N.SHARED_SYSTEM.EDMA.endian_in;
CONNECT114 C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT115 C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_big_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian; //<CHECK>
CONNECT116 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian; //Corrected
CONNECT117 C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness_big_endian; //Corrected
CONNECT118 C66XX_N.SHARED_SYSTEM.IPC.endian, C66XX_N.CPU_SYSTEM_0.CPU0_endianness; //<CHECK>
// INTERRUPT Connections
// System Interrupt Connections - INTC0
//GPIO
CONNECT119 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in0, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint16_opin;
CONNECT120 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in1, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint17_opin;
CONNECT121 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in2, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint18_opin;
CONNECT122 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in3, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint19_opin;
CONNECT123 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in4, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint20_opin;
CONNECT124 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in5, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint21_opin;
CONNECT125 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in6, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint22_opin;
CONNECT126 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in7, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint23_opin;
CONNECT127 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in8, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint24_opin;
CONNECT128 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in9, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint25_opin;
CONNECT129 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in10, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint26_opin;
CONNECT130 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in11, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint27_opin;
CONNECT131 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in12, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint28_opin;
CONNECT132 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in13, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint29_opin;
CONNECT133 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in14, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint30_opin;
CONNECT134 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in15, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint31_opin;
//EDMA
CONNECT135 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in16, C66XX_N.SHARED_SYSTEM.EDMA.errint_out_pin;
CONNECT136 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in22, C66XX_N.SHARED_SYSTEM.EDMA_gint_out_pin;
CONNECT137 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in24, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin0;
CONNECT138 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in25, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin1;
CONNECT139 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in26, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin2;
CONNECT140 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in27, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin3;
CONNECT141 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in28, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin4;
CONNECT142 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in29, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin5;
CONNECT143 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in30, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin6;
CONNECT144 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in31, C66XX_N.SHARED_SYSTEM.EDMA_int_out_pin7;
//UART_1
CONNECT145 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in40, C66XX_N.SHARED_SYSTEM.UART_1.uart_interrupt_out;
//SEMAPHORE2
CONNECT146 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in68, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin2;
CONNECT147 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in69, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin3;
CONNECT148 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in70, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin2;
CONNECT149 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in71, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin3;
//SRIO
CONNECT150 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in112, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr0;
CONNECT151 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in113, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr1;
CONNECT152 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in114, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr2;
CONNECT153 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in115, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr3;
CONNECT154 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in116, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr4;
CONNECT155 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in117, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr5;
CONNECT156 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in118, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr6;
CONNECT157 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in119, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr7;
CONNECT158 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in120, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr8;
CONNECT159 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in121, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr9;
CONNECT160 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in122, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr10;
CONNECT161 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in123, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr11;
CONNECT162 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in124, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr12;
CONNECT163 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in125, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr13;
CONNECT164 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in126, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr14;
CONNECT165 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in127, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr15;
//QMSS
CONNECT166 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_22_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in134;
CONNECT167 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_23_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in135;
CONNECT168 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_24_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in136;
CONNECT169 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_25_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in137;
CONNECT170 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_26_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in138;
CONNECT171 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_27_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in139;
CONNECT172 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_28_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in140;
CONNECT173 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_29_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in141;
CONNECT174 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_30_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in142;
CONNECT175 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_31_opin, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in175;
//VCP
CONNECT176 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in143, C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_INTR;
CONNECT177 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in144, C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_INTR;
CONNECT178 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in147, C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_DMA_REVT;
CONNECT179 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in148, C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_DMA_XEVT;
CONNECT180 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in149, C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_DMA_REVT;
CONNECT181 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in150, C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_DMA_XEVT;
//TIMERS
CONNECT182 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in145, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_12;
CONNECT183 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in146, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_34;
CONNECT184 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in151, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_12;
CONNECT185 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in152, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_34;
CONNECT186 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in153, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_12;
CONNECT187 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in154, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_34;
CONNECT188 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in162, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_12;
CONNECT189 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in163, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_34;
//INTD_TCP3D_A
CONNECT190 C66XX_N.SHARED_SYSTEM.INTD_TCP3D_A.intr_out_edge, C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in155;
//TCP3D
CONNECT191 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in157, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_revt0_opin;
CONNECT192 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in158, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_revt1_opin;
//UART_0
CONNECT193 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in164, C66XX_N.SHARED_SYSTEM.UART_0.uart_interrupt_out;
// System Interrupt Connections - INTC1
//GPIO
CONNECT194 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in0, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT195 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in1, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT196 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in2, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT197 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in3, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT198 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in4, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT199 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in5, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT200 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in6, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT201 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in7, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT202 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in17, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint16_opin;
CONNECT203 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in18, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint17_opin;
CONNECT204 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in19, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint18_opin;
CONNECT205 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in20, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint19_opin;
CONNECT206 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in21, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint20_opin;
CONNECT207 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in22, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint21_opin;
CONNECT208 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in47, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint22_opin;
CONNECT209 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in48, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint23_opin;
CONNECT210 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in117, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint24_opin;
CONNECT211 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in118, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint25_opin;
CONNECT212 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in121, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint26_opin;
CONNECT213 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in122, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint27_opin;
CONNECT214 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in124, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint28_opin;
CONNECT215 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in125, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint29_opin;
CONNECT216 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in126, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint30_opin;
CONNECT217 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in127, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint31_opin;
CONNECT218 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in128, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT219 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in129, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT220 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in130, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT221 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in131, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
//QUEUE_MANAGER
CONNECT222 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in24, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_16_opin;
CONNECT223 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in25, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_17_opin;
CONNECT224 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in26, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_18_opin;
CONNECT225 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in27, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_19_opin;
CONNECT226 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in28, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_20_opin;
CONNECT227 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in29, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_21_opin;
CONNECT228 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in30, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_22_opin;
CONNECT229 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in31, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_23_opin;
CONNECT230 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in32, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_24_opin;
CONNECT231 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in33, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_25_opin;
CONNECT232 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in34, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_26_opin;
CONNECT233 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in35, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_27_opin;
CONNECT234 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in36, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_28_opin;
CONNECT235 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in37, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_29_opin;
CONNECT236 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in38, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_30_opin;
CONNECT237 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in39, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_31_opin;
CONNECT238 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in137, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_0_opin;
CONNECT239 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in138, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_1_opin;
CONNECT240 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in139, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_2_opin;
CONNECT241 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in140, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_3_opin;
CONNECT242 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in141, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_4_opin;
CONNECT243 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in142, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_5_opin;
CONNECT244 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in143, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_6_opin;
CONNECT245 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in144, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_7_opin;
CONNECT246 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in145, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_8_opin;
CONNECT247 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in146, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_9_opin;
CONNECT248 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in147, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_10_opin;
CONNECT249 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in148, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_11_opin;
CONNECT250 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in149, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_12_opin;
CONNECT251 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in150, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_13_opin;
CONNECT252 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in151, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_14_opin;
CONNECT253 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in152, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_15_opin;
//SEMAPHORE
CONNECT254 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in58, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin0;
CONNECT255 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in59, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin1;
CONNECT256 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in60, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin2;
CONNECT257 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in61, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin3;
//SRIO
CONNECT258 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in93, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr0;
CONNECT259 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in94, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr1;
CONNECT260 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in95, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr2;
CONNECT261 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in96, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr3;
CONNECT262 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in97, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr4;
CONNECT263 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in98, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr5;
CONNECT264 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in99, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr6;
CONNECT265 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in100, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr7;
CONNECT266 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in101, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr8;
CONNECT267 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in102, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr9;
CONNECT268 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in103, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr10;
CONNECT269 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in104, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr11;
CONNECT270 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in105, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr12;
CONNECT271 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in106, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr13;
CONNECT272 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in107, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr14;
CONNECT273 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in108, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr15;
CONNECT274 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in109, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr16;
CONNECT275 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in110, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr17;
CONNECT276 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in111, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr18;
CONNECT277 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in112, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr19;
CONNECT278 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in113, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr20;
CONNECT279 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in114, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr21;
CONNECT280 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in115, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr22;
CONNECT281 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in116, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr23;
//VCP
CONNECT282 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in119, C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_INTR;
CONNECT283 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in120, C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_INTR;
//INTD_TCP3D_A
CONNECT284 C66XX_N.SHARED_SYSTEM.INTD_TCP3D_A.intr_out_edge, C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in123;
// System Interrupt Connections - INTC2
//GPIO
CONNECT285 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in0, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
CONNECT286 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in1, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
CONNECT287 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in2, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT288 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in3, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
CONNECT289 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in4, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT290 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in5, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT291 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in6, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT292 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in7, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
CONNECT293 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in8, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT294 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in9, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT295 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in10, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT296 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in11, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT297 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in12, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT298 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in13, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT299 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in14, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT300 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in15, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT301 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in25, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint16_opin;
CONNECT302 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in26, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint17_opin;
CONNECT303 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in27, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint18_opin;
CONNECT304 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in28, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint19_opin;
CONNECT305 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in29, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint20_opin;
CONNECT306 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in30, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint21_opin;
CONNECT307 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in33, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint22_opin;
CONNECT308 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in34, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint23_opin;
CONNECT309 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in45, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint24_opin;
CONNECT310 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in46, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint25_opin;
CONNECT311 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in47, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint26_opin;
CONNECT312 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in48, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint27_opin;
CONNECT313 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in64, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint28_opin;
CONNECT314 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in65, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint29_opin;
CONNECT315 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in66, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint30_opin;
CONNECT316 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in67, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint31_opin;
//TIMER64
CONNECT317 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in49, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_12;
CONNECT318 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in50, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_34;
CONNECT319 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in51, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_12;
CONNECT320 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in52, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_34;
CONNECT321 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in53, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_12;
CONNECT322 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in54, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_34;
CONNECT323 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in55, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_12;
CONNECT324 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in56, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_34;
CONNECT325 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in68, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_12;
CONNECT326 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in69, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_34;
CONNECT327 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in70, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_12;
CONNECT328 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in71, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_34;
// Host Interrupt Connections for INTC0
//! With CGEM_0
CONNECT329 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out0, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_22;
CONNECT330 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out1, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_23;
CONNECT331 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out2, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_24;
CONNECT332 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out3, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_25;
CONNECT333 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out4, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_26;
CONNECT334 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out5, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_27;
CONNECT335 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out6, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_28;
CONNECT336 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out7, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_29;
CONNECT337 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out8, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_30;
CONNECT338 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out9, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_31;
CONNECT339 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out10, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_92;
CONNECT340 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out11, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_93;
CONNECT341 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out40, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_56;
CONNECT342 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out41, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_57;
CONNECT343 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out42, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_58;
CONNECT344 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out43, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_59;
CONNECT345 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out44, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_60;
CONNECT346 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out45, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_61;
CONNECT347 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out46, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_62;
CONNECT348 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out47, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_63;
//! With CGEM_1
CONNECT349 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out20, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_22;
CONNECT350 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out21, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_23;
CONNECT351 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out22, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_24;
CONNECT352 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out23, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_25;
CONNECT353 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out24, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_26;
CONNECT354 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out25, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_27;
CONNECT355 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out26, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_28;
CONNECT356 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out27, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_29;
CONNECT357 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out28, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_30;
CONNECT358 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out29, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_31;
CONNECT359 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out30, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_92;
CONNECT360 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out31, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_93;
CONNECT361 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out40, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_56;
CONNECT362 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out41, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_57;
CONNECT363 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out42, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_58;
CONNECT364 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out43, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_59;
CONNECT365 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out44, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_60;
CONNECT366 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out45, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_61;
CONNECT367 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out46, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_62;
CONNECT368 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_out47, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_63;
// Host Interrupt Connections for INTC1
//! With EDMA
ONNECT481 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out0, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin43;
CONNECT369 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out1, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin44;
CONNECT370 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out2, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin45;
CONNECT371 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out3, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin46;
CONNECT372 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out4, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin47;
CONNECT373 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out5, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin48;
CONNECT374 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out6, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin49;
CONNECT375 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out7, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin50;
CONNECT376 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out8, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin51;
CONNECT377 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out9, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin52;
CONNECT378 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out10, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin53;
CONNECT379 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out11, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin54;
CONNECT380 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out12, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin55;
CONNECT381 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out13, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin56;
CONNECT382 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out14, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin57;
CONNECT383 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out15, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin58;
CONNECT384 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out16, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin59;
CONNECT385 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_out17, C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin60;
// Primary Interrupt Connections with CPU
//!CPU0
//SEMAPHORE
CONNECT386 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_15, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin0;
CONNECT387 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_16, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin0;
//SRIO
CONNECT388 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_20, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr16;
CONNECT389 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_21, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr20;
CONNECT390 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_112, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr18;
CONNECT391 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_114, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr22;
//QUEUE_MANAGER
CONNECT392 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_32, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT393 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_33, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT394 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_34, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT395 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_35, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT396 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_36, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT397 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_37, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT398 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_38, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT399 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_39, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT400 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_40, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT401 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_41, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT402 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_42, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT403 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_43, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT404 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_44, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT405 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_45, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT406 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_46, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT407 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_47, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT408 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_48, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_0_opin;
CONNECT409 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_49, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_4_opin;
CONNECT410 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_50, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_8_opin;
CONNECT411 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_51, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_12_opin;
CONNECT412 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_52, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_16_opin;
CONNECT413 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_53, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_20_opin;
CONNECT414 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_54, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_24_opin;
CONNECT415 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_55, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_28_opin;
CONNECT416 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_102, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_2_opin;
CONNECT417 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_103, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_6_opin;
CONNECT418 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_104, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_10_opin;
CONNECT419 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_105, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_14_opin;
CONNECT420 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_106, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_18_opin;
CONNECT421 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_107, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_22_opin;
CONNECT422 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_108, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_26_opin;
CONNECT423 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_109, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_30_opin;
//TIMERS
CONNECT424 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_64, C66XX_N.SHARED_SYSTEM.TIMER64_0_cpu_int_12;
CONNECT425 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_65, C66XX_N.SHARED_SYSTEM.TIMER64_0_cpu_int_34;
CONNECT426 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_66, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_12;
CONNECT427 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_67, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_34;
CONNECT428 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_68, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_12;
CONNECT429 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_69, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_34;
//GPIO
CONNECT430 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_72, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT431 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_73, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
CONNECT432 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_78, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT433 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_79, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT434 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_80, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT435 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_81, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
CONNECT436 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_82, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT437 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_83, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT438 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_84, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT439 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_85, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT440 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_86, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT441 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_87, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT442 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_88, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT443 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_89, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT444 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_91, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
//IPC
CONNECT445 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_90, C66XX_N.SHARED_SYSTEM.IPC_cpu_int_0;
//!CPU1
//SEMAPHORE
CONNECT446 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_15, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin1;
CONNECT447 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_16, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin1;
//SRIO
CONNECT448 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_20, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr17;
CONNECT449 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_21, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr21;
CONNECT450 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_112, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr19;
CONNECT451 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_114, C66XX_N.SHARED_SYSTEM.SRIO.srio_intdst_intr23;
//QUEUE_MANAGER
CONNECT452 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_32, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT453 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_33, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT454 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_34, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT455 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_35, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT456 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_36, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT457 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_37, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT458 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_38, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT459 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_39, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT460 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_40, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT461 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_41, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT462 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_42, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT463 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_43, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT464 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_44, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT465 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_45, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT466 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_46, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT467 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_47, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT468 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_48, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_1_opin;
CONNECT469 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_49, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_5_opin;
CONNECT470 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_50, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_9_opin;
CONNECT471 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_51, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_13_opin;
CONNECT472 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_52, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_17_opin;
CONNECT473 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_53, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_21_opin;
CONNECT474 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_54, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_25_opin;
CONNECT475 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_55, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_29_opin;
CONNECT476 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_102, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_3_opin;
CONNECT477 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_103, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_7_opin;
CONNECT478 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_104, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_11_opin;
CONNECT479 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_105, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_15_opin;
CONNECT480 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_106, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_19_opin;
CONNECT481 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_107, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_23_opin;
CONNECT482 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_108, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_27_opin;
CONNECT483 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_109, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_31_opin;
//TIMERS
CONNECT484 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_64, C66XX_N.SHARED_SYSTEM.TIMER64_1_cpu_int_12;
CONNECT485 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_65, C66XX_N.SHARED_SYSTEM.TIMER64_1_cpu_int_34;
CONNECT486 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_66, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_12;
CONNECT487 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_67, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_34;
CONNECT488 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_68, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_12;
CONNECT489 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_69, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_34;
//GPIO
CONNECT490 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_72, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT491 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_73, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
CONNECT492 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_78, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT493 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_79, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT494 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_80, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT495 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_81, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
CONNECT496 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_82, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT497 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_83, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT498 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_84, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT499 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_85, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT500 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_86, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT501 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_87, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT502 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_88, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT503 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_89, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT504 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_91, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
//IPC
CONNECT505 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_90, C66XX_N.SHARED_SYSTEM.IPC_cpu_int_1;
// Primary Interrupt Connections with EDMA
//TCP3D
CONNECT506 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin0, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_revt0_opin;
CONNECT507 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin1, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_revt1_opin;
//TIMER64
CONNECT508 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin2, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_12;
CONNECT509 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin3, C66XX_N.SHARED_SYSTEM.TIMER64_2_cpu_int_34;
CONNECT510 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin22, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_12;
CONNECT511 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin23, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_34;
CONNECT512 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin24, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_12;
CONNECT513 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin25, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_34;
CONNECT514 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin26, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_12;
CONNECT515 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin27, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_34;
CONNECT516 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin28, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_12;
CONNECT517 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin29, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_34;
CONNECT518 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin34, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_12;
CONNECT519 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin35, C66XX_N.SHARED_SYSTEM.TIMER64_3_cpu_int_34;
//GPIO
CONNECT520 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin6, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
CONNECT521 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin7, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
CONNECT522 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin8, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT523 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin9, C66XX_N.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
//VCP2
CONNECT524 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin10, C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_DMA_REVT;
CONNECT525 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin11, C66XX_N.SHARED_SYSTEM.VCP2_0.VCP_DMA_XEVT;
CONNECT526 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin12, C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_DMA_REVT;
CONNECT527 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin13, C66XX_N.SHARED_SYSTEM.VCP2_1.VCP_DMA_XEVT;
//SEMAPHORE
CONNECT528 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin18, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin0;
CONNECT529 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin19, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin1;
CONNECT530 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin20, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin2;
CONNECT531 C66XX_N.SHARED_SYSTEM.EDMA_evt_in_pin21, C66XX_N.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin3;
//! Connections of INTSEL with CPU
CONNECT532 System.C66XX_N.CPU_SYSTEM_0.CPU0.EXCEP, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_excep_out;
CONNECT533 System.C66XX_N.CPU_SYSTEM_0.CPU0.NMI, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_nmi_out;
CONNECT534 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT4, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int4_out;
CONNECT535 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT5, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int5_out;
CONNECT536 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT6, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int6_out;
CONNECT537 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT7, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int7_out;
CONNECT538 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT8, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int8_out;
CONNECT539 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT9, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int9_out;
CONNECT540 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT10, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int10_out;
CONNECT541 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT11, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int11_out;
CONNECT542 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT12, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int12_out;
CONNECT543 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT13, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int13_out;
CONNECT544 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT14, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int14_out;
CONNECT545 System.C66XX_N.CPU_SYSTEM_0.CPU0.INT15, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int15_out;
CONNECT546 System.C66XX_N.CPU_SYSTEM_0.CPU0cpu_idropped_out, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_idrop_in;
CONNECT547 System.C66XX_N.CPU_SYSTEM_1.CPU1.EXCEP, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_excep_out;
CONNECT548 System.C66XX_N.CPU_SYSTEM_1.CPU1.NMI, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_nmi_out;
CONNECT549 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT4, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int4_out;
CONNECT550 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT5, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int5_out;
CONNECT551 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT6, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int6_out;
CONNECT552 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT7, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int7_out;
CONNECT553 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT8, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int8_out;
CONNECT554 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT9, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int9_out;
CONNECT555 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT10, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int10_out;
CONNECT556 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT11, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int11_out;
CONNECT557 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT12, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int12_out;
CONNECT558 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT13, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int13_out;
CONNECT559 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT14, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int14_out;
CONNECT560 System.C66XX_N.CPU_SYSTEM_1.CPU1.INT15, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int15_out;
CONNECT561 System.C66XX_N.CPU_SYSTEM_1.CPU1cpu_idropped_out, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_idrop_in;
//! CDMA_INFRA connections
//! These pins setup loopback mode for the Streaming I/f
CONNECT562 C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_thread_mready_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_thread_mready_ipin;
CONNECT563 C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_thread_sready_ipin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_thread_sready_opin;
CONNECT564 C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_data_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_data_ipin;
CONNECT565 C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_data_accept_ipin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_data_accept_opin;
CONNECT566 System.C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_rx_teardown_req_opin, System.C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_rx_teardown_ack_ipin;
//! QUEUE_MANAGER with CDMA_INFRA
CONNECT567 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_qmgr_que_pend1_opin, C66XX_N.SHARED_SYSTEM.CDMA_INFRA.cdma_que_pend_ipin;
//! CDMA_INFRA connections
//****************************************************************************************************************************//
//! Exposing CPU boundary Pins to Pin-connect Plugin // //****************************************************************************************************************************//
CONNECT568 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.NMI, CPU0_NMI;
CONNECT569 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.NMI, CPU1_NMI;
CONNECT570 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT4, CPU0_INT4;
CONNECT571 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT5, CPU0_INT5;
CONNECT572 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT6, CPU0_INT6;
CONNECT573 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT7, CPU0_INT7;
CONNECT574 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT8, CPU0_INT8;
CONNECT575 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT9, CPU0_INT9;
CONNECT576 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT10, CPU0_INT10;
CONNECT577 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT11, CPU0_INT11;
CONNECT578 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT12, CPU0_INT12;
CONNECT579 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT13, CPU0_INT13;
CONNECT580 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT14, CPU0_INT14;
CONNECT581 C66XX_N.CPU_SYSTEM_0.CPU0.PINC, C66XX_N.CPU_SYSTEM_0.CPU0.INT15, CPU0_INT15;
CONNECT582 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT4, CPU1_INT4;
CONNECT583 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT5, CPU1_INT5;
CONNECT584 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT6, CPU1_INT6;
CONNECT585 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT7, CPU1_INT7;
CONNECT586 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT8, CPU1_INT8;
CONNECT587 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT9, CPU1_INT9;
CONNECT588 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT10, CPU1_INT10;
CONNECT589 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT11, CPU1_INT11;
CONNECT590 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT12, CPU1_INT12;
CONNECT591 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT13, CPU1_INT13;
CONNECT592 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT14, CPU1_INT14;
CONNECT593 C66XX_N.CPU_SYSTEM_1.CPU1.PINC, C66XX_N.CPU_SYSTEM_1.CPU1.INT15, CPU1_INT15;
//! NMI connections from IPC
CONNECT594 C66XX_N.CPU_SYSTEM_0.CPU0.NMI, C66XX_N.SHARED_SYSTEM.IPC_cpu_nmi_0;
CONNECT595 C66XX_N.CPU_SYSTEM_1.CPU1.NMI, C66XX_N.SHARED_SYSTEM.IPC_cpu_nmi_1;
//! Connections for INTD_TCP3D_A
CONNECT596 C66XX_N.SHARED_SYSTEM.INTD_TCP3D_A.ip_intr_level0, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_error_intr_p0_opin;
CONNECT597 C66XX_N.SHARED_SYSTEM.INTD_TCP3D_A.ip_intr_level1, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_error_intr_p1_opin;
CONNECT598 C66XX_N.SHARED_SYSTEM.INTD_TCP3D_A.ip_eoi, C66XX_N.SHARED_SYSTEM.TCP3D_A.tcp3d_eoi_vector_opin;
CONNECT599 C66XX_N.SHARED_SYSTEM.INTD_TCP3D_A.reset_in, C66XX_N.SHARED_SYSTEM_INTF.reset_out;
// CP_INTC Debug view fix
CONNECT600 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_endian_in, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT601 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_endian_in, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT602 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_endian_in, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT603 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC0_CFG.memtr_read_opin;
CONNECT604 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC0_CFG.memtr_write_opin;
CONNECT605 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_dbg_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC0_CFG.memtr_dbg_read_opin;
CONNECT606 C66XX_N.SHARED_SYSTEM.CP_INTC0.cp_intc_dbg_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC0_CFG.memtr_dbg_write_opin;
CONNECT607 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC1_CFG.memtr_read_opin;
CONNECT608 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC1_CFG.memtr_write_opin;
CONNECT609 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_dbg_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC1_CFG.memtr_dbg_read_opin;
CONNECT610 C66XX_N.SHARED_SYSTEM.CP_INTC1.cp_intc_dbg_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC1_CFG.memtr_dbg_write_opin;
CONNECT611 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC2_CFG.memtr_read_opin;
CONNECT612 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC2_CFG.memtr_write_opin;
CONNECT613 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_dbg_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC2_CFG.memtr_dbg_read_opin;
CONNECT614 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_dbg_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.INTC2_CFG.memtr_dbg_write_opin;
CONNECT615 C66XX_N.SHARED_SYSTEM.IPC.ici_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.ICI_CFG.memtr_read_opin;
CONNECT616 C66XX_N.SHARED_SYSTEM.IPC.ici_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.ICI_CFG.memtr_write_opin;
CONNECT617 C66XX_N.SHARED_SYSTEM.IPC.ici_dbg_read_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.ICI_CFG.memtr_dbg_read_opin;
CONNECT618 C66XX_N.SHARED_SYSTEM.IPC.ici_dbg_write_in, C66XX_N.SHARED_SYSTEM.INTERCONNECT.ICI_CFG.memtr_dbg_write_opin;
//TIMER64
CONNECT619 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in49, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_12;
CONNECT620 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in50, C66XX_N.SHARED_SYSTEM.TIMER64_4_cpu_int_34;
CONNECT621 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in51, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_12;
CONNECT622 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in52, C66XX_N.SHARED_SYSTEM.TIMER64_5_cpu_int_34;
CONNECT623 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in53, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_12;
CONNECT624 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in54, C66XX_N.SHARED_SYSTEM.TIMER64_6_cpu_int_34;
CONNECT625 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in55, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_12;
CONNECT626 C66XX_N.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in56, C66XX_N.SHARED_SYSTEM.TIMER64_7_cpu_int_34;
// L1D and L1P connection for CGEM program path
CONNECT627 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT628 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT629 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT630 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
// L1D and L1P connection for CGEM Data path
CONNECT631 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT632 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT633 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT634 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, 0x00F00000, 0x00F07FFF, 0;
// Tag Ram connections
CONNECT635 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.dmc_tag_ram_read, C66XX_N.CPU_SYSTEM_0.CPU0dmc_tag_ram_read;
CONNECT636 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.pmc_tag_ram_read, C66XX_N.CPU_SYSTEM_0.CPU0pmc_tag_ram_read;
CONNECT637 C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.umc_tag_ram_read, C66XX_N.CPU_SYSTEM_0.CPU0umc_tag_ram_read;
CONNECT638 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.dmc_tag_ram_read, C66XX_N.CPU_SYSTEM_1.CPU1dmc_tag_ram_read;
CONNECT639 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.pmc_tag_ram_read, C66XX_N.CPU_SYSTEM_1.CPU1pmc_tag_ram_read;
CONNECT640 C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.umc_tag_ram_read, C66XX_N.CPU_SYSTEM_1.CPU1umc_tag_ram_read;
// Memory Viewer Connections
CONNECT641 C66XX_N.CPU_SYSTEM_0.CPU0l1d_cache_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1D_cache_dbg_read;
CONNECT642 C66XX_N.CPU_SYSTEM_0.CPU0l1d_cache_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1D_cache_dbg_write;
CONNECT643 C66XX_N.CPU_SYSTEM_0.CPU0l1d_sram_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1D_sram_dbg_read;
CONNECT644 C66XX_N.CPU_SYSTEM_0.CPU0l1d_sram_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1D_sram_dbg_write;
CONNECT645 C66XX_N.CPU_SYSTEM_0.CPU0l1p_cache_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1P_cache_dbg_read;
CONNECT646 C66XX_N.CPU_SYSTEM_0.CPU0l1p_cache_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1P_cache_dbg_write;
CONNECT647 C66XX_N.CPU_SYSTEM_0.CPU0l1p_sram_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1P_sram_dbg_read;
CONNECT648 C66XX_N.CPU_SYSTEM_0.CPU0l1p_sram_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L1P_sram_dbg_write;
CONNECT649 C66XX_N.CPU_SYSTEM_0.CPU0l2_cache_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L2_cache_dbg_read;
CONNECT650 C66XX_N.CPU_SYSTEM_0.CPU0l2_cache_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L2_cache_dbg_write;
CONNECT651 C66XX_N.CPU_SYSTEM_0.CPU0l2_sram_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L2_sram_dbg_read;
CONNECT652 C66XX_N.CPU_SYSTEM_0.CPU0l2_sram_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.L2_sram_dbg_write;
CONNECT653 C66XX_N.CPU_SYSTEM_0.CPU0ext_mem_dbg_read_in, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.EXTMEM_ext_dbg_read;
CONNECT654 C66XX_N.CPU_SYSTEM_0.CPU0ext_mem_dbg_write_out, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.EXTMEM_ext_dbg_write;
CONNECT655 C66XX_N.CPU_SYSTEM_1.CPU1l1d_cache_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1D_cache_dbg_read;
CONNECT656 C66XX_N.CPU_SYSTEM_1.CPU1l1d_cache_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1D_cache_dbg_write;
CONNECT657 C66XX_N.CPU_SYSTEM_1.CPU1l1d_sram_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1D_sram_dbg_read;
CONNECT658 C66XX_N.CPU_SYSTEM_1.CPU1l1d_sram_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1D_sram_dbg_write;
CONNECT659 C66XX_N.CPU_SYSTEM_1.CPU1l1p_cache_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1P_cache_dbg_read;
CONNECT660 C66XX_N.CPU_SYSTEM_1.CPU1l1p_cache_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1P_cache_dbg_write;
CONNECT661 C66XX_N.CPU_SYSTEM_1.CPU1l1p_sram_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1P_sram_dbg_read;
CONNECT662 C66XX_N.CPU_SYSTEM_1.CPU1l1p_sram_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L1P_sram_dbg_write;
CONNECT663 C66XX_N.CPU_SYSTEM_1.CPU1l2_cache_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L2_cache_dbg_read;
CONNECT664 C66XX_N.CPU_SYSTEM_1.CPU1l2_cache_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L2_cache_dbg_write;
CONNECT665 C66XX_N.CPU_SYSTEM_1.CPU1l2_sram_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L2_sram_dbg_read;
CONNECT666 C66XX_N.CPU_SYSTEM_1.CPU1l2_sram_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.L2_sram_dbg_write;
CONNECT667 C66XX_N.CPU_SYSTEM_1.CPU1ext_mem_dbg_read_in, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.EXTMEM_ext_dbg_read;
CONNECT668 C66XX_N.CPU_SYSTEM_1.CPU1ext_mem_dbg_write_out, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.EXTMEM_ext_dbg_write;
//For GAUSS
//Functional Interconnect Related
CONNECT669 C66XX_N.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.memtr_mif_opin, 0x0, 0xFFFFFFFF, 0;
CONNECT670 C66XX_N.SHARED_SYSTEM.INTERCONNECT.MSMC_PATH.memtr_read_ipin, C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.memtr_read_opin;
CONNECT671 C66XX_N.SHARED_SYSTEM.INTERCONNECT.MSMC_PATH.memtr_write_ipin, C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.memtr_write_opin;
CONNECT672 C66XX_N.SHARED_SYSTEM.INTERCONNECT.MSMC_PATH.memtr_dbg_read_ipin, C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT673 C66XX_N.SHARED_SYSTEM.INTERCONNECT.MSMC_PATH.memtr_dbg_write_ipin, C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT674 C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT675 C66XX_N.SHARED_SYSTEM.MEMTR_MSMC_Adaptor.MT_MIF2SSI.is_little_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT676 C66XX_N.SHARED_SYSTEM.INTERCONNECT.DDR_SLAVE2.memtr_read_opin, C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.memtr_read_ipin;
CONNECT677 C66XX_N.SHARED_SYSTEM.INTERCONNECT.DDR_SLAVE2.memtr_write_opin, C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.memtr_write_ipin;
CONNECT678 C66XX_N.SHARED_SYSTEM.INTERCONNECT.DDR_SLAVE2.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.memtr_dbg_read_ipin;
CONNECT679 C66XX_N.SHARED_SYSTEM.INTERCONNECT.DDR_SLAVE2.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.memtr_dbg_write_ipin;
CONNECT680 C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_N.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
CONNECT681 C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT682 C66XX_N.SHARED_SYSTEM.MEMTR_FLATMEM_36BIT_Adaptor.MT_SSI2MMAP.is_little_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT683 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM0_SLV.memtr_read_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.memtr_read_ipin;
CONNECT684 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM0_SLV.memtr_write_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.memtr_write_ipin;
CONNECT685 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM0_SLV.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.memtr_dbg_read_ipin;
CONNECT686 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM0_SLV.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.memtr_dbg_write_ipin;
CONNECT687 C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0, 0xFFFFFFFF, 0;
CONNECT688 C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT689 C66XX_N.SHARED_SYSTEM.MEMTR_CGEM0_Slv_Adaptor.MT_SSI2MMAP.is_little_endian_ipin, C66XX_N.CPU_SYSTEM_0.CPU0_endianness;
CONNECT690 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM1_SLV.memtr_read_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.memtr_read_ipin;
CONNECT691 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM1_SLV.memtr_write_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.memtr_write_ipin;
CONNECT692 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM1_SLV.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.memtr_dbg_read_ipin;
CONNECT693 C66XX_N.SHARED_SYSTEM.INTERCONNECT.CGEM1_SLV.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.memtr_dbg_write_ipin;
CONNECT694 C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0, 0xFFFFFFFF, 0;
CONNECT695 C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT696 C66XX_N.SHARED_SYSTEM.MEMTR_CGEM1_Slv_Adaptor.MT_SSI2MMAP.is_little_endian_ipin, C66XX_N.CPU_SYSTEM_1.CPU1_endianness;
//! QUEUE_MANAGER with CDMA_SRIO
CONNECT697 C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_qmgr_que_pend2_opin, C66XX_N.SHARED_SYSTEM.CDMA_SRIO.cdma_que_pend_ipin;
CONNECT698 System.C66XX_N.CPU_SYSTEM_0.CPU0.EXCEP, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.security_exception_output_opin;
CONNECT699 System.C66XX_N.CPU_SYSTEM_1.CPU1.EXCEP, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.security_exception_output_opin;
CONNECT700 System.C66XX_N.CPU_SYSTEM_0.CPU0.exc_out, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.exception_in;
CONNECT701 System.C66XX_N.CPU_SYSTEM_1.CPU1.exc_out, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.exception_in;
CONNECT702 System.C66XX_N.CPU_SYSTEM_0.CPU0.inum_out, System.C66XX_N.CPU_SYSTEM_0.CGEM_SSI_0.cgem_inum_ipin;
CONNECT703 System.C66XX_N.CPU_SYSTEM_1.CPU1.inum_out, System.C66XX_N.CPU_SYSTEM_1.CGEM_SSI_1.cgem_inum_ipin;
//QM DMA
CONNECT704 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_DMA.memtr_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_read_ipin;
CONNECT705 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_DMA.memtr_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_write_ipin;
CONNECT706 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_DMA.memtr_dbg_read_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_dbg_read_ipin;
CONNECT707 C66XX_N.SHARED_SYSTEM.INTERCONNECT.QUEUE_MANAGER_DMA.memtr_dbg_write_opin, C66XX_N.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_dbg_write_ipin;
CONNECT708 System.C66XX_N.SHARED_SYSTEM_INTF.reset_out, C66XX_N.SHARED_SYSTEM.UART_0.uart_reset_in;
CONNECT709 System.C66XX_N.SHARED_SYSTEM_INTF.reset_out, C66XX_N.SHARED_SYSTEM.UART_1.uart_reset_in;
CONNECT710 System.C66XX_N.SHARED_SYSTEM.DSP_BOOT_ROM.MT_SSI2FLATMEM.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT711 System.C66XX_N.SHARED_SYSTEM.DSP_BOOT_ROM.MT_SSI2FLATMEM.memtr_reset_ipin, System.SimBridge.global_reset_list;
// BUSCONNECT1 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.UART_0. , System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_0.;
// BUSCONNECT2 MEMTR_S_M, System.C66XX_N.SHARED_SYSTEM.UART_1. , System.C66XX_N.SHARED_SYSTEM.INTERCONNECT.UART_1.;
END System;
// --- PDATS enablement -------------------//
SECTION PDATS_TRACE_ON_CORE0;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_N.CPU_SYSTEM_0.CPU0_mem_map, System.C66XX_N.CPU_SYSTEM_0.CPU0.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE0;
SECTION PDATS_TRACE_ON_CORE1;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_N.CPU_SYSTEM_1.CPU1_mem_map, System.C66XX_N.CPU_SYSTEM_1.CPU1.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE1;
// -------------------- END PDATS enablement -------------------//
// ----- END of simulator configuration file -------------
Hi Weihua,
It appears like you have attached C6657 config file and not c6678_pv.cfg config file. Can you attach the correct file.
Also can you provide couple of more information,.
1. I believe you are using simulator on linux platform, right?
2. In order to try and reproduce your scenario, can you describe what DSP cores are involved in the DMA xfer?
regards,
Shesha.
Hi Sheshadri,
Sorry, I attached the wrong file earlier. The correct file is below after the questions. Thanks.
1. Yes, I am using CCS on Linux.
2. The one I am currently testing is from core1 to core0. In earlier tries, I also tried core0 to core1, didn't work either.
tisim_c6678_pv.cfg
//---------------------------------------------------------------------------
/// C66xx_S Platform Functional Simulator Configuration File
// Copyright (c) 2007-2008 Texas Instruments Incorporated
// Version 1.0.0//--------------------------------------------------------------------------------
MODULE GTI_INFO;
GTI_DVR_NAME tisim_adv_sb.dvr;
SERVER_AUTO_RUN ON;
END GTI_INFO;
//MODULE GTI;
// ECCSETUP OFF;
// CACHE_MEM_VIEWER ON;
//END GTI;
//MODULE OTIS;
// DYNAMIC_LIB ../../../bin/components/spkfc6xxxd.so;
//END OTIS;
//MODULE C6X;
// CHIP CGEMp75_CORE;
// SIMBRIDGE_DLL ../../../bin/components/sim_server.so;
//END C6X;
MODULE SIMBRIDGE;
ADVANCE_TYPE CYCLE_ADVANCE_WITH_INSTR_HALT;
//
// To enable simulator construction logs uncomment MODULE SIMBRIGE, END SIMBRIDGE and the line having "FILE_LOG ON"
// The options here are
// 1. ON - will generate the default log files, declare_intf.log, connect_intf.log and sim_integration.log
// 2. <file name> - will generate all the log information into the specified file name.
// 3. OFF - logging disabled
//
// FILE_LOG ON;
// Send global break status to GTIs of the processors
// that are forced to halt on other processor break point
SEND_GLOBAL_BREAK_STATUS ON;
SIMBRIDGE_DLL ../../../bin/components/sim_server.so;
END SIMBRIDGE;
MODULE System;
DSP CPU0,CPU1,CPU2,CPU3,CPU4,CPU5,CPU6,CPU7;
DEBUGVIEW CPU0,CPU1,CPU2,CPU3,CPU4,CPU5,CPU6,CPU7;
SUB_MODULES C66XX_S;
MODULE C66XX_S;
SUB_MODULES CPU_SYSTEM_0, CPU_SYSTEM_1, CPU_SYSTEM_2, CPU_SYSTEM_3, CPU_SYSTEM_4, CPU_SYSTEM_5, CPU_SYSTEM_6, CPU_SYSTEM_7, SHARED_SYSTEM;
MODULE CPU_SYSTEM_0;
SUB_MODULES CPU0, CGEM_SSI_0;
MODULE CPU0;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 0;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE0;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH0;
END CPU0;
MODULE CGEM_SSI_0;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU0;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 0;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 0;
PRIV_ID 0;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_0;
END CPU_SYSTEM_0;
MODULE CPU_SYSTEM_1;
SUB_MODULES CPU1, CGEM_SSI_1;
MODULE CPU1;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 1;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE1;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH1;
END CPU1;
MODULE CGEM_SSI_1;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU1;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 1;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 1;
PRIV_ID 1;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_1;
END CPU_SYSTEM_1;
MODULE CPU_SYSTEM_2;
SUB_MODULES CPU2, CGEM_SSI_2;
MODULE CPU2;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 2;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE2;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH2;
END CPU2;
MODULE CGEM_SSI_2;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU2;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 2;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 2;
PRIV_ID 2;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_2;
END CPU_SYSTEM_2;
MODULE CPU_SYSTEM_3;
SUB_MODULES CPU3, CGEM_SSI_3;
MODULE CPU3;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 3;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE3;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH3;
END CPU3;
MODULE CGEM_SSI_3;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU3;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 3;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 3;
PRIV_ID 3;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_3;
END CPU_SYSTEM_3;
MODULE CPU_SYSTEM_4;
SUB_MODULES CPU4, CGEM_SSI_4;
MODULE CPU4;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 4;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE4;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH4;
END CPU4;
MODULE CGEM_SSI_4;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU4;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 4;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 4;
PRIV_ID 4;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_4;
END CPU_SYSTEM_4;
MODULE CPU_SYSTEM_5;
SUB_MODULES CPU5, CGEM_SSI_5;
MODULE CPU5;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 5;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE5;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH5;
END CPU5;
MODULE CGEM_SSI_5;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU5;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 5;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 5;
PRIV_ID 5;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_5;
END CPU_SYSTEM_5;
MODULE CPU_SYSTEM_6;
SUB_MODULES CPU6, CGEM_SSI_6;
MODULE CPU6;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 6;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE6;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH6;
END CPU6;
MODULE CGEM_SSI_6;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU6;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 6;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 6;
PRIV_ID 6;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_6;
END CPU_SYSTEM_6;
MODULE CPU_SYSTEM_7;
SUB_MODULES CPU7, CGEM_SSI_7;
MODULE CPU7;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/spkfc6xxxd.so;
//! "C" interfaces to the DLL
INIT_FUNC SIM_init;
INIT_DONE_FUNC SIM_init_done;
CONNECT_FUNC SIM_megamodule_connect;
SUPPORTS_MEM_STAT ON;
QUIT_FUNC SIM_quit;
//! Debug "C" interfaces
TS_CREATE_FUNC SIM_ts_create;
TS_DESTROY_FUNC SIM_ts_destroy;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE CPU;
CLOCK_FREQ 1000; //1000 MHz/1 GHz
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
USE_SEPARATE_PROG_MEM_MAP ON;
MISSED_INTERRUPT_WARNING OFF;
//*****************************//
//! CPU Architecture Entries !//
//*****************************//
//! ISA (JOULE).
ISA CGEMp75_CORE;
C66X_INSTR_PROFILING ON;
//********************//
//! ISTP reset value. //
//********************//
ISTP_RESET_VALUE 0x00800000; //L2 SRAM Start address
//! The Resource conflict Detection feature is not supported in the Joule ISA
RESOURCE_CONFLICT_DETECTION OFF;
//! Memgamodule ID.
MM_ID 7;
MODULE HPS2;
MAX_BLOCK_SIZE_HINT 65536; // 64KB, in bytes
BLOCK_HIT_THRESHOLD 2000;
SPLOOP OFF;
CODE_COVERAGE ON;
END HPS2;
// To enable PDATS trace uncomment the next line
// IMPORT PDATS_TRACE_ON_CORE7;
// TO disable register trace collection, comment out all line from MODULE CALLBACK_INTF_REMOVE to END CALLBACK_INTF_REMOVE
// or rename CALLBACK_INTF to CALLBACK_INTF_REMOVE<some other string> (CALLBACK_INTF_REMOVE__ for eg.,)
MODULE CALLBACK_INTF;
DLL_PATH ../../../bin/components/reg_mem_trace_intf_v2.so;
CALLBACK ON;
CYCLE_INFO ON;
PC_INFO ON;
PC_OPCODE_INFO OFF; // OFF by default
PC_MAX_OPCODE_SIZE 4; // in bytes
REG_INFO ON;
REGS_SELECTED A4,B3,B4,A6,B6,B15;
REG_SIZE 4; // in bytes
REG_INDEX_SIZE 1; // in bytes
MEM_READ_INFO ON;
MEM_WRITE_INFO ON;
// size of buffer to hold trace data before transfering to disk file, in bytes
BUFFER_SIZE 1048576; // 1MB
START_COLLECTION 0; //
END CALLBACK_INTF;
IMPORT PATCH7;
END CPU7;
MODULE CGEM_SSI_7;
TYPE PERIPHERAL;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_cgem_ssi.so;
CPU_VIEW CPU7;
INIT_FUNC cgem_ssi_init;
INIT_DONE_FUNC cgem_ssi_init_done;
CONNECT_FUNC cgem_ssi_connect_done;
QUIT_FUNC cgem_ssi_quit;
MM_ID 7;
NUM_MM 8;
BOOT_MEMORY_MAP 1; //<CHECK> Is "1" by default
L1D_START_ADDRESS 0x00F00000;
L1D_SIZE 0x8000;
L1P_START_ADDRESS 0x00E00000;
L1P_SIZE 0x8000;
L2_START_ADDRESS 0x00800000;
L2_SIZE 0x80000;
CGEM_REG_START 0x01800000; //Excluding the starting reserved region
CGEM_REG_END 0x01BFFFFF;
XMC_CONFIG_START 0x08000000;
XMC_CONFIG_END 0x0801FFFF;
MASTER_ID 7;
PRIV_ID 7;
SECURE_MODE 0;
CACHE_BYPASS 0;
MODULE DMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00F00000;
END DMC;
MODULE PMC;
CACHE_SIZE 0x8000;
MEMORY_SIZE 0x8000;
SRAM_START_ADDRESS 0x00E00000;
END PMC;
MODULE UMC;
//CACHE_SIZE 0x100000;
CACHE_SIZE 0x00000;
MAX_CACHE_SIZE 512KB;
MEMORY_SIZE 0x80000;
SRAM_START_ADDRESS 0x00800000;
END UMC;
END CGEM_SSI_7;
END CPU_SYSTEM_7;
MODULE SHARED_SYSTEM;
SUB_MODULES
SHARED_SYSTEM_INTF,
MSMC,
BOOT_ROM,
TIMER64_0, //Watch Dog for Core0
TIMER64_1, //Watch Dog for Core1
TIMER64_2, //Watch Dog for Core2
TIMER64_3, //Watch Dog for Core3
TIMER64_4, //Watch Dog for Core4
TIMER64_5, //Watch Dog for Core5
TIMER64_6, //Watch Dog for Core6
TIMER64_7, //Watch Dog for Core7
TIMER64_8,
TIMER64_9,
TIMER64_10,
TIMER64_11,
TIMER64_12,
TIMER64_13,
TIMER64_14,
TIMER64_15,
EDMA_0,
EDMA_1,
EDMA_2,
CP_INTC0,
MEMTR_CP_INTC0_Config,
CP_INTC1,
MEMTR_CP_INTC1_Config,
CP_INTC2,
MEMTR_CP_INTC2_Config,
CP_INTC3,
MEMTR_CP_INTC3_Config,
SEMAPHORE,
IPC,
MEMTR_IPC_Config,
GPIO,
QUEUE_MANAGER,
CDMA_INFRA,
SRIO, //SRIO sub-system
MEMTR_SRIO_Config,
MEMTR_SRIO_Slave,
CDMA_SRIO,
MEMTR_CDMA_SRIO_Config,
MEMTR_CDMA_SRIO_Master,
SWITCHSS, //PA sub-system
MEMTR_SWITCHSS_Config,
MEMTR_SWITCHSS_SERDES_Config,
EMAC_ADAPTOR,
PASS,
MEMTR_PASS_Master,
MIF_TO_FUNC_PASS,
CDMA_PASS,
MEMTR_CDMA_PASS_Config,
MEMTR_CDMA_PASS_Master,
PCIE,
MEMTR_GPIO_Config,
MEMTR_SMS,
MEMTR_SES,
MEMTR_SEMAPHORE_Config,
MEMTR_QM_DMA_Config,
MEMTR_QM_Config,
MEMTR_QM_PDSP_Command,
//MEMTR_QM_High_Accumulator,
MEMTR_QM_PDSP_Master,
MEMTR_CDMA_INFRA_Config,
MEMTR_CDMA_INFRA_Master,
MEMTR_PCIE_Slave,
SSI2SOCK_PORT0, //for SRIO
FLATMEM_36BIT,
PSC,
MIF_TO_FUNC_PSC;
MODULE SHARED_SYSTEM_INTF;
TYPE SHARED;
SSI_VER SC_1.0.0; // new ssi module
CLOCK_FREQ 1000;
RUN_GRAN 0.000125; // 50 Run granularity (unit is msec)
DLL ../../../bin/components/sim_shared_system_intf.so;
INIT_FUNC shared_system_intf_init_func;
INIT_DONE_FUNC shared_system_intf_init_done_func;
QUIT_FUNC shared_system_intf_quit_func;
END SHARED_SYSTEM_INTF;
MODULE MSMC;
NAME msmc;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_msmc_ssi.so;
INIT_FUNC msmc_ssi_init_func;
INIT_DONE_FUNC msmc_ssi_init_done_func;
QUIT_FUNC msmc_ssi_quit_func;
NO_OF_CORES 8;
RAM_START_ADDRESS 0x0C000000;
RAM_SIZE 0x400000;
CFG_START_ADDRESS 0x0BC00000;
END MSMC;
MODULE BOOT_ROM;
TYPE SHARED;
TERMINAL ROM;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_mif_bridge.so;
CLOCK_ENABLED NO;
INIT_FUNC flatmem_init_func;
INIT_DONE_FUNC flatmem_init_done_func;
QUIT_FUNC flatmem_quit_func;
END BOOT_ROM;
MODULE TIMER64_0;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_0;
MODULE TIMER64_1;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_1;
MODULE TIMER64_2;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_2;
MODULE TIMER64_3;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_3;
MODULE TIMER64_4;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_4;
MODULE TIMER64_5;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_5;
MODULE TIMER64_6;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_6;
MODULE TIMER64_7;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG ON;
END TIMER64_7;
MODULE TIMER64_8;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_8;
MODULE TIMER64_9;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_9;
MODULE TIMER64_10;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_10;
MODULE TIMER64_11;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_11;
MODULE TIMER64_12;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_12;
MODULE TIMER64_13;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_13;
MODULE TIMER64_14;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_14;
MODULE TIMER64_15;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/sim_timer64.so;
//! "C" interfaces to the DLL
INIT_FUNC timer64_init_func;
INIT_DONE_FUNC timer64_init_done_func;
QUIT_FUNC timer64_quit_func;
CLOCK_DIVIDE 6;
// Timer64P Configuration.Enables the Hilander features.
VERSION TIMER64P;
// Watchdog Capability for TIMER64
WATCH_DOG OFF;
END TIMER64_15;
MODULE EDMA_0;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/sim_edma.so;
//! "C" interfaces to the DLL
INIT_FUNC dma_init_func;
INIT_DONE_FUNC dma_init_done_func;
CONNECT_FUNC dma_connect_func;
QUIT_FUNC dma_quit_func;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE SHARED;
//*********************************//
//! EDMA v3 Architecture Entries !//
//*********************************//
CLOCK_DIVIDE_RATIO 2;
NUM_DMA_CHANNELS 16;
NUM_QDMA_CHANNELS 8;
NUM_INT_CHANNELS 16;
NUM_PARAM_ENTRIES 128;
NUM_EVENT_QUEUES 2;
NUM_TCS 2;
MP_EXISTS YES;
CHANNEL_MAP_EXISTS YES;
NUM_REGIONS 8;
END EDMA_0;
MODULE EDMA_1;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/sim_edma.so;
//! "C" interfaces to the DLL
INIT_FUNC dma_init_func;
INIT_DONE_FUNC dma_init_done_func;
CONNECT_FUNC dma_connect_func;
QUIT_FUNC dma_quit_func;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE SHARED;
//*********************************//
//! EDMA v3 Architecture Entries !//
//*********************************//
CLOCK_DIVIDE_RATIO 3;
NUM_DMA_CHANNELS 64;
NUM_QDMA_CHANNELS 8;
NUM_INT_CHANNELS 64;
NUM_PARAM_ENTRIES 512;
NUM_EVENT_QUEUES 4;
NUM_TCS 4;
MP_EXISTS YES;
CHANNEL_MAP_EXISTS YES;
NUM_REGIONS 8;
END EDMA_1;
MODULE EDMA_2;
//********************************//
//! Simulation Specific Entries !//
//********************************//
//! DLL
DLL ../../../bin/components/sim_edma.so;
//! "C" interfaces to the DLL
INIT_FUNC dma_init_func;
INIT_DONE_FUNC dma_init_done_func;
CONNECT_FUNC dma_connect_func;
QUIT_FUNC dma_quit_func;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! Module Type.
TYPE SHARED;
//*********************************//
//! EDMA v3 Architecture Entries !//
//*********************************//
CLOCK_DIVIDE_RATIO 3;
NUM_DMA_CHANNELS 64;
NUM_QDMA_CHANNELS 8;
NUM_INT_CHANNELS 64;
NUM_PARAM_ENTRIES 512;
NUM_EVENT_QUEUES 4;
NUM_TCS 4;
MP_EXISTS YES;
CHANNEL_MAP_EXISTS YES;
NUM_REGIONS 8;
END EDMA_2;
MODULE CP_INTC0;
//! Module Name.
NAME CP_INTC0;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 160; //<CHECK>
NUMBER_OF_CHANNELS 76;
NUMBER_OF_HOST_INTERRUPT 76; //<CHECK>
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
HOST_CHANNEL_MAP29 29;
HOST_CHANNEL_MAP30 30;
HOST_CHANNEL_MAP31 31;
HOST_CHANNEL_MAP32 32;
HOST_CHANNEL_MAP33 33;
HOST_CHANNEL_MAP34 34;
HOST_CHANNEL_MAP35 35;
HOST_CHANNEL_MAP36 36;
HOST_CHANNEL_MAP37 37;
HOST_CHANNEL_MAP38 38;
HOST_CHANNEL_MAP39 39;
HOST_CHANNEL_MAP40 40;
HOST_CHANNEL_MAP41 41;
HOST_CHANNEL_MAP42 42;
HOST_CHANNEL_MAP43 43;
HOST_CHANNEL_MAP44 44;
HOST_CHANNEL_MAP45 45;
HOST_CHANNEL_MAP46 46;
HOST_CHANNEL_MAP47 47;
HOST_CHANNEL_MAP48 48;
HOST_CHANNEL_MAP49 49;
HOST_CHANNEL_MAP50 50;
HOST_CHANNEL_MAP51 51;
HOST_CHANNEL_MAP52 52;
HOST_CHANNEL_MAP53 53;
HOST_CHANNEL_MAP54 54;
HOST_CHANNEL_MAP55 55;
HOST_CHANNEL_MAP56 56;
HOST_CHANNEL_MAP57 57;
HOST_CHANNEL_MAP58 58;
HOST_CHANNEL_MAP59 59;
HOST_CHANNEL_MAP60 60;
HOST_CHANNEL_MAP61 61;
HOST_CHANNEL_MAP62 62;
HOST_CHANNEL_MAP63 63;
HOST_CHANNEL_MAP64 64;
HOST_CHANNEL_MAP65 65;
HOST_CHANNEL_MAP66 66;
HOST_CHANNEL_MAP67 67;
HOST_CHANNEL_MAP68 68;
HOST_CHANNEL_MAP69 69;
HOST_CHANNEL_MAP70 70;
HOST_CHANNEL_MAP71 71;
HOST_CHANNEL_MAP72 72;
HOST_CHANNEL_MAP73 73;
HOST_CHANNEL_MAP74 74;
HOST_CHANNEL_MAP75 75;
END CP_INTC0;
MODULE CP_INTC1;
//! Module Name.
NAME CP_INTC1;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 160; //<CHECK>
NUMBER_OF_CHANNELS 76;
NUMBER_OF_HOST_INTERRUPT 76; //<CHECK>
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
HOST_CHANNEL_MAP29 29;
HOST_CHANNEL_MAP30 30;
HOST_CHANNEL_MAP31 31;
HOST_CHANNEL_MAP32 32;
HOST_CHANNEL_MAP33 33;
HOST_CHANNEL_MAP34 34;
HOST_CHANNEL_MAP35 35;
HOST_CHANNEL_MAP36 36;
HOST_CHANNEL_MAP37 37;
HOST_CHANNEL_MAP38 38;
HOST_CHANNEL_MAP39 39;
HOST_CHANNEL_MAP40 40;
HOST_CHANNEL_MAP41 41;
HOST_CHANNEL_MAP42 42;
HOST_CHANNEL_MAP43 43;
HOST_CHANNEL_MAP44 44;
HOST_CHANNEL_MAP45 45;
HOST_CHANNEL_MAP46 46;
HOST_CHANNEL_MAP47 47;
HOST_CHANNEL_MAP48 48;
HOST_CHANNEL_MAP49 49;
HOST_CHANNEL_MAP50 50;
HOST_CHANNEL_MAP51 51;
HOST_CHANNEL_MAP52 52;
HOST_CHANNEL_MAP53 53;
HOST_CHANNEL_MAP54 54;
HOST_CHANNEL_MAP55 55;
HOST_CHANNEL_MAP56 56;
HOST_CHANNEL_MAP57 57;
HOST_CHANNEL_MAP58 58;
HOST_CHANNEL_MAP59 59;
HOST_CHANNEL_MAP60 60;
HOST_CHANNEL_MAP61 61;
HOST_CHANNEL_MAP62 62;
HOST_CHANNEL_MAP63 63;
HOST_CHANNEL_MAP64 64;
HOST_CHANNEL_MAP65 65;
HOST_CHANNEL_MAP66 66;
HOST_CHANNEL_MAP67 67;
HOST_CHANNEL_MAP68 68;
HOST_CHANNEL_MAP69 69;
HOST_CHANNEL_MAP70 70;
HOST_CHANNEL_MAP71 71;
HOST_CHANNEL_MAP72 72;
HOST_CHANNEL_MAP73 73;
HOST_CHANNEL_MAP74 74;
HOST_CHANNEL_MAP75 75;
END CP_INTC1;
MODULE CP_INTC2;
//! Module Name.
NAME CP_INTC2;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 160; //<CHECK>
NUMBER_OF_CHANNELS 52;
NUMBER_OF_HOST_INTERRUPT 52; //<CHECK>
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
HOST_CHANNEL_MAP29 29;
HOST_CHANNEL_MAP30 30;
HOST_CHANNEL_MAP31 31;
HOST_CHANNEL_MAP32 32;
HOST_CHANNEL_MAP33 33;
HOST_CHANNEL_MAP34 34;
HOST_CHANNEL_MAP35 35;
HOST_CHANNEL_MAP36 36;
HOST_CHANNEL_MAP37 37;
HOST_CHANNEL_MAP38 38;
HOST_CHANNEL_MAP39 39;
HOST_CHANNEL_MAP40 40;
HOST_CHANNEL_MAP41 41;
HOST_CHANNEL_MAP42 42;
HOST_CHANNEL_MAP43 43;
HOST_CHANNEL_MAP44 44;
HOST_CHANNEL_MAP45 45;
HOST_CHANNEL_MAP46 46;
HOST_CHANNEL_MAP47 47;
HOST_CHANNEL_MAP48 48;
HOST_CHANNEL_MAP49 49;
HOST_CHANNEL_MAP50 50;
HOST_CHANNEL_MAP51 51;
END CP_INTC2;
MODULE CP_INTC3;
//! Module Name.
NAME CP_INTC3;
//! Module Type.
TYPE SHARED;
//! System Integrator version compliance number
SSI_VER SC_1.0.0;
//! DLL
DLL ../../../bin/components/tisim_intc_cpintc_pv_ssi.so;
//! "C" interfaces to the DLL
INIT_FUNC cp_intc_init;
INIT_DONE_FUNC cp_init_done;
QUIT_FUNC cp_quit;
//! Module Configuration
NUMBER_OF_INTERRUPTS 80; //<CHECK>
NUMBER_OF_CHANNELS 40;
NUMBER_OF_HOST_INTERRUPT 40; //<CHECK>
NUMBER_OF_DEBUG_INTERRUPT 0;
VECTORING 0;
VECTORING_FULL 0;
NESTING_SUPPORT 1;
HOST_TYPE GENERIC;
REVISION 0x4E820000;
HOST_CHANNEL_MAP0 0;
HOST_CHANNEL_MAP1 1;
HOST_CHANNEL_MAP2 2;
HOST_CHANNEL_MAP3 3;
HOST_CHANNEL_MAP4 4;
HOST_CHANNEL_MAP5 5;
HOST_CHANNEL_MAP6 6;
HOST_CHANNEL_MAP7 7;
HOST_CHANNEL_MAP8 8;
HOST_CHANNEL_MAP9 9;
HOST_CHANNEL_MAP10 10;
HOST_CHANNEL_MAP11 11;
HOST_CHANNEL_MAP12 12;
HOST_CHANNEL_MAP13 13;
HOST_CHANNEL_MAP14 14;
HOST_CHANNEL_MAP15 15;
HOST_CHANNEL_MAP16 16;
HOST_CHANNEL_MAP17 17;
HOST_CHANNEL_MAP18 18;
HOST_CHANNEL_MAP19 19;
HOST_CHANNEL_MAP20 20;
HOST_CHANNEL_MAP21 21;
HOST_CHANNEL_MAP22 22;
HOST_CHANNEL_MAP23 23;
HOST_CHANNEL_MAP24 24;
HOST_CHANNEL_MAP25 25;
HOST_CHANNEL_MAP26 26;
HOST_CHANNEL_MAP27 27;
HOST_CHANNEL_MAP28 28;
HOST_CHANNEL_MAP29 29;
HOST_CHANNEL_MAP30 30;
HOST_CHANNEL_MAP31 31;
HOST_CHANNEL_MAP32 32;
HOST_CHANNEL_MAP33 33;
HOST_CHANNEL_MAP34 34;
HOST_CHANNEL_MAP35 35;
HOST_CHANNEL_MAP36 36;
HOST_CHANNEL_MAP37 37;
HOST_CHANNEL_MAP38 38;
HOST_CHANNEL_MAP39 39;
END CP_INTC3;
MODULE SEMAPHORE;
TYPE SHARED;
SSI_VER SSI_1.1;
NAME semaphore2;
DLL ../../../bin/components/semaphore2.so;
INIT_FUNC semaphore2_init;
INIT_DONE_FUNC semaphore2_init_done;
QUIT_FUNC semaphore2_quit;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 PID, 0x48021200; //"12" as per RTL design
INPUT3 NUM_MASTERS, 8;
INPUT4 NUM_RESOURCES, 32;
END USER_INPUTS;
END SEMAPHORE;
MODULE IPC;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_inter_core_interrupt.so;
INIT_FUNC inter_core_interrupt_init_func;
INIT_DONE_FUNC inter_core_interrupt_init_done_func;
QUIT_FUNC inter_core_interrupt_quit_func;
CLOCK_DIVIDE_RATIO 6;
NO_OF_CORES 8;
WAITING_TIME_WINDOW 8; //<CHECK>
NMIGR_SUPPORT ON; //Enabling NMIGR support
NMI_PULSE_WINDOW 1;
NMIGR_START_OFFSET 0; //Indicates the offset from the start of the Inter-core memory region for inter-core NMIGR
IPCGR_START_OFFSET 16;
IPCAR_START_OFFSET 32;
ENABLE_WARNING_MSGS OFF;
END IPC;
MODULE GPIO;
NAME gpio;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_gpio_pv.so;
INIT_FUNC gpio_init;
INIT_DONE_FUNC gpio_init_done;
QUIT_FUNC gpio_quit;
MODULE INTERFACES;
// MIF_TO_FUNC_GPIO => GPIO
CONNECT1 System.C66XX_S.SHARED_SYSTEM.GPIO.gpio_cfg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.GPIO.gpio_cfg_read_ipin,System.C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT3 System.C66XX_S.SHARED_SYSTEM.GPIO.gpio_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.GPIO.gpio_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.GPIO.gpio_reset_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.GPIO.gpio_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 NUM_GPINT_PINS, 16;
INOUT3 PID, 0x44831105;
END USER_INPUTS;
END GPIO;
MODULE QUEUE_MANAGER;
NAME queue_manager;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/qmss.so;
//CPU_VIEW <<CPU_MODULE_NAME>>; //Update this entry with the CPU module name in the system
INIT_FUNC qmss_init;
INIT_DONE_FUNC qmss_init_done;
QUIT_FUNC qmss_quit;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME , SHARED;
INPUT2 NUM_QM , 1;
INPUT3 QUEUES_PER_QM , 8192;
INPUT4 MEM_REGN_PER_QM , 20;
INPUT5 NUM_PDSP , 2;
INPUT6 NUM_INTD , 1;
INPUT7 NUM_TIMER , 2;
INPUT8 NUM_MCDMA , 1;
INPUT9 LINKRAM_BASE , 0x00080000;
INPUT10 LINKRAM_INDEXES , 16384;
INPUT11 QM_CFG_BASE , 0x00068000;
INPUT12 QM_CFG_OFFSET , 0x00002000;
INPUT13 QM_DESC_BASE , 0x0006a000;
INPUT14 QM_DESC_OFFSET , 0x00002000;
INPUT15 QM_QUE_BASE , 0x00020000;
INPUT16 QM_QUE_OFFSET , 0x00020000;
INPUT17 QM_PEEK_BASE , 0x00000000;
INPUT18 QM_PEEK_OFFSET , 0x00020000;
INPUT19 QM_STATUS_BASE , 0x00062000;
INPUT20 QM_STATUS_OFFSET , 0x00000400;
INPUT21 QM_PROXY_BASE , 0x00040000;
INPUT22 QM_PROXY_OFFSET , 0x00020000;
INPUT23 PDSP_GBL_SCRTCH_BASE , 0x00000000; //na on Ny/Sh/Tn/Aptn
INPUT24 PDSP_GBL_SCRTCH_SIZE , 0x00000000; //na on Ny/Sh/Tn/Aptn
INPUT25 PDSP_LCL_SCRTCH_BASE , 0x000b8000;
INPUT26 PDSP_LCL_SCRTCH_OFFSET, 0x00004000;
INPUT27 PDSP_REG_BASE , 0x0006E000;
INPUT28 PDSP_REG_OFFSET , 0x00001000;
INPUT29 PDSP_DBG_BASE , 0x000b0000;
INPUT30 PDSP_DBG_OFFSET , 0x00001000;
INPUT31 PDSP_IRAM_BASE , 0x00060000;
INPUT32 PDSP_IRAM_OFFSET , 0x00001000;
INPUT33 PDSP_SCRTCH_EVEN_SIZE , 0x00004000;
INPUT34 PDSP_SCRTCH_ODD_SIZE , 0x00002000;
INPUT35 QM_INTD_BASE , 0x000a0000;
INPUT36 QM_INTD_OFFSET , 0x00001000;
INPUT37 QM_TIMER_BASE , 0x000a8000;
INPUT38 QM_TIMER_OFFSET , 0x00000800;
INPUT39 QM_MCDMA_BASE , 0x00090000;
INPUT40 QM_MCDMA_OFFSET , 0x00000800;
INPUT41 TOTAL_CFG_SPACE , 0x000c0000;
INPUT42 INTC_1ST_QNUM , 650;
INPUT43 INTC_NUM_QUEUES , 22;
INPUT44 STARVATION_1ST_QNUM , 736;
INPUT45 STARVATION_NUM_QUEUES , 64;
INPUT46 TIMER_TICK , 7;
INPUT47 TIMER_RESOLUTION , 1000;
INPUT48 NUM_PKTDMA , 8; //Num pktDMA defs to follow
INPUT49 PKTDMA_1_TXQ , 800; //Infra1
INPUT50 PKTDMA_1_NUMQ , 32;
INPUT51 PKTDMA_2_TXQ , 512; //AIF2
INPUT52 PKTDMA_2_NUMQ , 128;
INPUT53 PKTDMA_3_TXQ , 640; //PASS
INPUT54 PKTDMA_3_NUMQ , 9;
INPUT55 PKTDMA_4_TXQ , 672; //SRIO
INPUT56 PKTDMA_4_NUMQ , 16;
INPUT57 PKTDMA_5_TXQ , 688; //FFTC_A
INPUT58 PKTDMA_5_NUMQ , 4;
INPUT59 PKTDMA_6_TXQ , 692; //FFTC_B
INPUT60 PKTDMA_6_NUMQ , 4;
INPUT61 PKTDMA_7_TXQ , 864; //FFTC_C
INPUT62 PKTDMA_7_NUMQ , 4;
INPUT63 PKTDMA_8_TXQ , 868; //BCP
INPUT64 PKTDMA_8_NUMQ , 8;
// INPUT65 DEBUG_LOG, qmss_debug_log.txt;
END USER_INPUTS;
END QUEUE_MANAGER;
MODULE CDMA_INFRA;
NAME cdma_qm;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/cdma.so;
INIT_FUNC cdma_init;
INIT_DONE_FUNC cdma_init_done;
QUIT_FUNC cdma_quit;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS; //changed as per Dave's mail
INPUT1 CPU_NAME , SHARED;
INPUT2 NUM_RX_CHANNELS , 32;
INPUT3 NUM_TX_CHANNELS , 32;
INPUT4 NUM_RX_FLOWS , 64;
INPUT5 RX_FIFO_SIZE , 32;
INPUT6 TX_FIFO_SIZE , 33; //(+1 for CDMA) as per Dave's mail
INPUT7 FIFO_DESC_SIZE , 8;
INPUT8 RX_FIFO_DEPTH , 32;
INPUT9 TX_FIFO_DEPTH , 48;
INPUT10 TX_CHUNK_READ , 128;
INPUT11 GLOBAL_CFG_OFFSET, 0x0006c000;
INPUT12 TX_CHAN_CFG_OFFSET, 0x0006c400;
INPUT13 RX_CHAN_CFG_OFFSET, 0x0006c800;
INPUT14 TX_SCHED_CFG_OFFSET, 0x0006cc00;
INPUT15 RX_FLOW_CFG_OFFSET, 0x0006d000;
INPUT16 QM_QUE_MMR_BASE , 0x34020000; //As per Dave's mail
INPUT17 FIRST_HW_QNUM , 800;
INPUT18 PACKET_OFFSET , 0;
INPUT19 PACKET_TAG , 0;
INPUT20 TX_SCHED_BYPASS , 0;
INPUT21 TX_DESCRIPTOR_RELEASE , 0;
INPUT22 LOOPBACK_MODE , 1;
INPUT23 PAYLOAD_TRANSPARENCY , 1;
INPUT24 CYCLE_APPROX_MODE, 0;
INPUT25 QM_POP_DELAY, 30;
INPUT26 QM_PUSH_DELAY, 45;
INPUT27 MEM_RW_DELAY, 1;
INPUT28 CLK_DIV, 3;
// INPUT29 DEBUG_LOG, CDMA_qmss_debug_log.txt;
END USER_INPUTS;
END CDMA_INFRA;
MODULE SSI2SOCK_PORT0;
NAME ssi2sock;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/ssi2sock.so;
INIT_FUNC ssi2sock_init;
INIT_DONE_FUNC ssi2sock_init_done;
QUIT_FUNC ssi2sock_quit;
MODULE INTERFACES;
//SSI connections to CPU and other peripheral;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_reset, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_receive_data, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_opin_port0;
CONNECT3 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_send_data, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ipin_port0;
// Propogate the error to every CPU model.
CONNECT4 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_error_opin, System.C66XX_S.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_error_opin, System.C66XX_S.CPU_SYSTEM_1.CPU1.error_intf_ssi;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_error_opin, System.C66XX_S.CPU_SYSTEM_2.CPU2.error_intf_ssi;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.SSI2SOCK_PORT0.SSI2SOCK_error_opin, System.C66XX_S.CPU_SYSTEM_3.CPU3.error_intf_ssi;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 SOCK, OFF;
INPUT2 SOCK_PORT, 2048;
INPUT3 MAX_NUM_BYTES_PER_SOCK_RECV, 16560; // Number of bytes attempted to receive
// for every Socket receive call
// Assuming each SRIO packet contains 4140
// bytes (max), the simulator is configured to
// handle upto 4 SRIO packets, in one socket
// read call.
INPUT4 RECV_FIFO_LENGTH, 10; // Fifo length. Each fifo entry can
// hold MAX_NUM_BYTES_PER_SOCK_RECV bytes
INPUT5 CPU_NAME, SHARED;
INPUT6 SOCK_PROTOCOL, TCP;
INPUT7 SOCK_TYPE, SERVER;
END USER_INPUTS;
END SSI2SOCK_PORT0;
MODULE SRIO;
NAME srio;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_srio.so;
INIT_FUNC srio_init;
INIT_DONE_FUNC srio_init_done;
QUIT_FUNC srio_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_reset, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_big_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian;
//These pins setup the Streaming interfaces
CONNECT3 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tstrm_thread_mready_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_thread_mready_ipin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tstrm_thread_sready_ipin, System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_thread_sready_opin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tstrm_data_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_data_ipin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tstrm_data_accept_ipin, System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_rstrm_data_accept_opin;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_thread_mready_opin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rstrm_thread_mready_ipin;
CONNECT8 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_thread_sready_ipin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rstrm_thread_sready_opin;
CONNECT9 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_data_opin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rstrm_data_ipin;
CONNECT10 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_tstrm_data_accept_ipin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rstrm_data_accept_opin;
// CFG and DBG read/write pins
CONNECT11 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_cfg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT12 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_cfg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT13 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_cfg_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT14 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_cfg_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_dbg_write_opin;
// Data region interface
CONNECT15 System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_read_opin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_dma_read_ipin;
CONNECT16 System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_write_opin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_dma_write_ipin;
CONNECT17 System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_dbg_read_opin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_dma_dbg_read_ipin;
CONNECT18 System.C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_dbg_write_opin, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_dma_dbg_write_ipin;
// Connect SRIO output ports and ready pins to inputs to loopback for testing
//CONNECT19 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_opin_port0, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ipin_port0;
CONNECT19 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_opin_port1, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ipin_port1;
CONNECT20 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_opin_port2, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ipin_port2;
CONNECT21 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_opin_port3, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ipin_port3;
//CONNECT23 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port0, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port0;
CONNECT22 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port1, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port1;
CONNECT23 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port2, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port2;
CONNECT24 System.C66XX_S.SHARED_SYSTEM.SRIO.srio_rx_ready_opin_port3, System.C66XX_S.SHARED_SYSTEM.SRIO.srio_tx_ready_ack_ipin_port3;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 CLK_DIV, 3;
// INPUT3 FILE_LOG, srio_dbg;
END USER_INPUTS;
END SRIO;
MODULE CDMA_SRIO;
NAME cdma_srio;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/cdma.so;
INIT_FUNC cdma_init;
INIT_DONE_FUNC cdma_init_done;
QUIT_FUNC cdma_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_reset_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian;
//These connections should be changed to connect the Tx Sched. to AIF or QMSS.
//CONNECT3 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_tx_scheduler_ipin, MainCPU.cdmatb_tx_scheduler_opin;
//CONNECT4 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_tx_scheduler_opin, MainCPU.cdmatb_tx_scheduler_ipin;
//These pins allow the CDMA to read/write memory.
CONNECT3 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_mstr_read_opin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_read_ipin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_mstr_write_opin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_write_ipin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_cfg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_cfg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT8 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT9 System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_rx_teardown_req_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_rx_teardown_ack_ipin;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 NUM_RX_CHANNELS, 16;
INPUT3 NUM_TX_CHANNELS, 16;
INPUT4 NUM_RX_FLOWS, 20;
INPUT5 RX_FIFO_SIZE, 1024;
INPUT6 TX_FIFO_SIZE, 1025; // +1 is for CDMA internal usage
INPUT7 FIFO_DESC_SIZE, 8;
INPUT8 RX_FIFO_DEPTH, 16;
INPUT9 TX_FIFO_DEPTH, 16;
INPUT10 TX_CHUNK_READ, 1024;
INPUT11 GLOBAL_CFG_OFFSET, 0x00001000;
INPUT12 TX_CHAN_CFG_OFFSET, 0x00001400;
INPUT13 RX_CHAN_CFG_OFFSET, 0x00001800;
INPUT14 TX_SCHED_CFG_OFFSET,0x00001c00;
INPUT15 RX_FLOW_CFG_OFFSET, 0x00002000;
INPUT16 QM_QUE_MMR_BASE, 0x34020000;
INPUT17 FIRST_HW_QNUM, 672;
INPUT18 PACKET_OFFSET, 1;
INPUT19 PACKET_TAG, 0;
INPUT20 TX_SCHED_BYPASS, 0;
INPUT21 TX_DESCRIPTOR_RELEASE, 1;
INPUT22 LOOPBACK_MODE, 0;
INPUT23 PAYLOAD_TRANSPARENCY, 0;
INPUT24 CYCLE_APPROX_MODE, 0;
INPUT25 QM_POP_DELAY, 30;
INPUT26 QM_PUSH_DELAY, 45;
INPUT27 MEM_RW_DELAY, 1;
INPUT28 CLK_DIV, 3;
//INPUT29 DEBUG_LOG , C:\CDMA_srio_Debug.log;
END USER_INPUTS;
END CDMA_SRIO;
MODULE SWITCHSS;
NAME switchss;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/switchss.so;
// CPU_VIEW MainCPU; //Update this entry with the CPU module name in the system
INIT_FUNC switchss_init;
INIT_DONE_FUNC switchss_init_done;
QUIT_FUNC switchss_quit;
MODULE INTERFACES;
//SSI connections to CPU and other peripheral;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_big_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_vbusp_reset_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT3 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_regs_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_regs_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_regs_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_regs_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_serdes_regs_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT8 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_serdes_regs_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT9 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_serdes_regs_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT10 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_memtr_serdes_regs_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_dbg_write_opin;
//CONNECT11 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii0_tx_data_gen_opin, System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii1_rx_data_gen_ipin;
// CONNECT12 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii0_rx_data_gen_ipin, System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii1_tx_data_gen_opin;
//CONNECT1 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_stat_intr0_opin, MainCPU.switchsstb_stat_intr0_ipin;
//CONNECT2 System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_stat_intr1_opin, MainCPU.switchsstb_stat_intr1_ipin;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 SWITCHSS_IDVER , 0x101010;
INPUT2 SGMII0_IDVER , 0x101010;
INPUT3 SGMII1_IDVER , 0x101010;
INPUT4 CPSW_IDVER , 0x101010;
INPUT5 SL1_IDVER , 0x101010;
INPUT6 SL2_IDVER , 0x101010;
INPUT7 ALE_IDVER , 0x101010;
INPUT8 NO_EMACS , 0x2; //Two EMACs required in this model
INPUT9 CPU_NAME , SHARED; //Update this entry with the CPU module name in the system
END USER_INPUTS;
END SWITCHSS;
MODULE EMAC_ADAPTOR;
NAME emac_adatpor;
SSI_VER SSI_1.1;
TYPE SHARED;
DLL ../../../bin/components/emac_adaptor.so;
//CPU_VIEW SHARED;
INIT_FUNC emac_adaptor_init;
INIT_DONE_FUNC emac_adaptor_init_done;
QUIT_FUNC emac_adaptor_quit;
MODULE INTERFACES;
//SSI connections to CPU and other peripheral;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_reset, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_receive_data_port0, System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii0_tx_data_gen_opin;
CONNECT3 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_send_data_port0, System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii0_rx_data_gen_ipin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_receive_data_port1, System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii1_tx_data_gen_opin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_send_data_port1, System.C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_sgmii1_rx_data_gen_ipin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_error_opin,System.C66XX_S.CPU_SYSTEM_0.CPU0.error_intf_ssi;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_error_opin,System.C66XX_S.CPU_SYSTEM_1.CPU1.error_intf_ssi;
CONNECT8 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_error_opin,System.C66XX_S.CPU_SYSTEM_2.CPU2.error_intf_ssi;
CONNECT9 System.C66XX_S.SHARED_SYSTEM.EMAC_ADAPTOR.EMAC_ADAPTOR_error_opin,System.C66XX_S.CPU_SYSTEM_3.CPU3.error_intf_ssi;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME, SHARED;
INPUT2 ADAPTOR, OFF;
INPUT3 NUMBER_OF_PORTS,2;
INPUT4 NETWORK_ADAPTOR, Broadcom;
INPUT5 MAC_ADDRESS_PORT0, 00-1C-BF-36-25-AF;
INPUT6 MAC_ADDRESS_PORT1, 00-21-86-81-A8-F0;
INPUT7 MAC_CRC, ON;
// INPUT8 LOG_FILE, c:\emac_log.txt;
END USER_INPUTS;
END EMAC_ADAPTOR;
MODULE PASS;
TYPE SHARED;
SSI_VER SSI_1.1;
NAME PASS;
DLL ../../../bin/components/tisim_pass.so;
INIT_FUNC pass_init;
INIT_DONE_FUNC pass_init_done;
QUIT_FUNC pass_quit;
MODULE INTERFACES;
//REMOVED CLOCK PIN CONNECTION, PASS NOW USES SCHEDULER
// CONNECT1 System.C66XX_S.SHARED_SYSTEM.PASS.pass_clock_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.clock_out;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.PASS.pass_reset_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.PASS.pass_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
//These pins setup the Streaming interfaces
CONNECT3 System.C66XX_S.SHARED_SYSTEM.PASS.pass_tstrm_cppi_mready_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_rstrm_thread_mready_ipin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.PASS.pass_tstrm_cppi_sready_ipin, System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_rstrm_thread_sready_opin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.PASS.pass_tstrm_cppi_data_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_rstrm_data_ipin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.PASS.pass_tstrm_cppi_data_accept_ipin, System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_rstrm_data_accept_opin;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_tstrm_thread_mready_opin, System.C66XX_S.SHARED_SYSTEM.PASS.pass_rstrm_cppi_mready_ipin;
CONNECT8 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_tstrm_thread_sready_ipin, System.C66XX_S.SHARED_SYSTEM.PASS.pass_rstrm_cppi_sready_opin;
CONNECT9 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_tstrm_data_opin, System.C66XX_S.SHARED_SYSTEM.PASS.pass_rstrm_cppi_data_ipin;
CONNECT10 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_tstrm_data_accept_ipin, System.C66XX_S.SHARED_SYSTEM.PASS.pass_rstrm_cppi_data_accept_opin;
CONNECT11 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_rx_teardown_req_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_rx_teardown_ack_ipin;
// CFG and DBG read/write pins
CONNECT12 System.C66XX_S.SHARED_SYSTEM.PASS.pass_cfg_read_req_ipin, System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_read_opin;
CONNECT13 System.C66XX_S.SHARED_SYSTEM.PASS.pass_cfg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_write_opin;
CONNECT14 System.C66XX_S.SHARED_SYSTEM.PASS.pass_dbg_read_req_ipin, System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT15 System.C66XX_S.SHARED_SYSTEM.PASS.pass_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_dbg_write_opin;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 cpu_freq_mhz, 1000;
INPUT2 pass_freq_mhz, 350;
INPUT3 sass_freq_mhz, 350;
INPUT4 CPU_NAME, SHARED;
//INPUT5 log_file, pass.log;
END USER_INPUTS;
END PASS;
MODULE CDMA_PASS;
NAME cdma_pass;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/cdma.so;
INIT_FUNC cdma_init;
INIT_DONE_FUNC cdma_init_done;
QUIT_FUNC cdma_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_reset_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian;
//These connections should be changed to connect the Tx Sched. to AIF or QMSS.
//CONNECT3 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_tx_scheduler_ipin, MainCPU.cdmatb_tx_scheduler_opin;
//CONNECT4 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_tx_scheduler_opin, MainCPU.cdmatb_tx_scheduler_ipin;
//These pins allow the CDMA to read/write memory.
CONNECT3 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_mstr_read_opin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_read_ipin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_mstr_write_opin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_write_ipin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_cfg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_cfg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT7 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT8 System.C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_dbg_write_opin;
END INTERFACES;
//User Inputs to be passed from CPU to the peripheral model
MODULE USER_INPUTS;
INPUT1 CPU_NAME , SHARED;
INPUT2 NUM_RX_CHANNELS, 24;
INPUT3 NUM_TX_CHANNELS, 9;
INPUT4 NUM_RX_FLOWS, 32;
INPUT5 RX_FIFO_SIZE, 9216;
INPUT6 TX_FIFO_SIZE, 9217; // +1 is for CDMA internal usage
INPUT7 FIFO_DESC_SIZE, 64;
INPUT8 RX_FIFO_DEPTH, 1;
INPUT9 TX_FIFO_DEPTH, 1;
INPUT10 TX_CHUNK_READ, 9216;
INPUT11 GLOBAL_CFG_OFFSET, 0x00004000;
INPUT12 TX_CHAN_CFG_OFFSET, 0x00004400;
INPUT13 RX_CHAN_CFG_OFFSET, 0x00004800;
INPUT14 TX_SCHED_CFG_OFFSET, 0x00004c00;
INPUT15 RX_FLOW_CFG_OFFSET, 0x00005000;
INPUT16 QM_QUE_MMR_BASE, 0x34020000;
INPUT17 FIRST_HW_QNUM, 640;
INPUT18 PACKET_OFFSET, 0;
INPUT19 PACKET_TAG, 0;
INPUT20 TX_SCHED_BYPASS, 0;
INPUT21 TX_DESCRIPTOR_RELEASE, 0;
INPUT22 LOOPBACK_MODE, 0;
INPUT23 PAYLOAD_TRANSPARENCY , 1;
INPUT24 CYCLE_APPROX_MODE, 0;
INPUT25 QM_POP_DELAY, 30;
INPUT26 QM_PUSH_DELAY, 45;
INPUT27 MEM_RW_DELAY, 1;
INPUT28 CLK_DIV, 3;
//INPUT29 DEBUG_LOG , C:\CDMA_pass.log;
END USER_INPUTS;
END CDMA_PASS;
MODULE PCIE;
NAME pciess;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_pciess.so;
INIT_FUNC pciess_init;
INIT_DONE_FUNC pciess_init_done;
QUIT_FUNC pciess_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.PCIE.pciess_reset, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.PCIE.pciess_big_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian;
CONNECT3 System.C66XX_S.SHARED_SYSTEM.PCIE.pciess_slv_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_read_opin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.PCIE.pciess_slv_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_write_opin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.PCIE.pciess_slv_dbg_read_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.PCIE.pciess_slv_dbg_write_ipin, System.C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_dbg_write_opin;
// NOTE:
// Master interface not modeled.
// Interrupt functionality is not modeled. So, not connected.
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 PID , 0x4e300000;
INPUT2 CLK_DIV , 3;
INPUT3 CFG_TYPE, 0;
INPUT4 CPU_NAME, SHARED;
INPUT5 CFG_BASE, 0x21800000;
END USER_INPUTS;
END PCIE;
//GPIO Connections
MODULE MEMTR_GPIO_Config;
NAME memtr_gpio_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_GPIO_Config;
MODULE MEMTR_SMS;
NAME MEMTR_SMS;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SMS;
MODULE MEMTR_SES;
NAME MEMTR_SES;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SES;
MODULE MEMTR_SEMAPHORE_Config;
NAME memtr_semaphore_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SEMAPHORE_Config;
MODULE MEMTR_QM_Config;
NAME memtr_qm_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_QM_Config;
MODULE MEMTR_QM_DMA_Config;
NAME memtr_qm_dma_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_QM_DMA_Config;
MODULE MEMTR_QM_PDSP_Command;
NAME memtr_qm_pdsp_command;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_QM_PDSP_Command;
MODULE MEMTR_QM_PDSP_Master;
NAME memtr_qm_pdsp_master;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_QM_PDSP_Master;
MODULE MEMTR_CDMA_INFRA_Config;
NAME memtr_cdma_qm_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CDMA_INFRA_Config;
MODULE MEMTR_CDMA_INFRA_Master;
NAME memtr_cdma_qm_master;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_CDMA_INFRA_Master;
MODULE MEMTR_SRIO_Config;
NAME memtr_srio_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SRIO_Config;
MODULE MEMTR_SRIO_Slave;
NAME memtr_srio_slave;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SRIO_Slave;
MODULE MEMTR_CDMA_SRIO_Config;
NAME memtr_srio_cdma_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CDMA_SRIO_Config;
MODULE MEMTR_CDMA_SRIO_Master;
NAME memtr_cdma_qm_master;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_CDMA_SRIO_Master;
MODULE MEMTR_SWITCHSS_Config;
NAME memtr_emac_sgmii_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SWITCHSS_Config;
MODULE MEMTR_SWITCHSS_SERDES_Config;
NAME memtr_emac_sgmii_serdes_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_SWITCHSS_SERDES_Config;
MODULE MIF_TO_FUNC_PASS;
NAME memtr_pass_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
TERMINAL MT_MIF2SSI;
END MIF_TO_FUNC_PASS;
MODULE MEMTR_PASS_Master;
NAME memtr_pass_master;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_PASS_Master;
MODULE MEMTR_CDMA_PASS_Config;
NAME memtr_cdma_pass_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CDMA_PASS_Config;
MODULE MEMTR_CDMA_PASS_Master;
NAME memtr_cdma_pass_master;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_SSI2MMAP;
END MEMTR_CDMA_PASS_Master;
MODULE MEMTR_PCIE_Slave;
NAME memtr_pcie_slave;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_PCIE_Slave;
MODULE MEMTR_CP_INTC0_Config;
NAME memtr_cp_intc0_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CP_INTC0_Config;
MODULE MEMTR_CP_INTC1_Config;
NAME memtr_cp_intc1_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CP_INTC1_Config;
MODULE MEMTR_CP_INTC2_Config;
NAME memtr_cp_intc2_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CP_INTC2_Config;
MODULE MEMTR_CP_INTC3_Config;
NAME memtr_cp_intc3_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_CP_INTC3_Config;
MODULE MEMTR_IPC_Config;
NAME memtr_ipc_config;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
//-- Entry-point
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
//-- Configurable parameters
TERMINAL MT_MIF2SSI;
END MEMTR_IPC_Config;
MODULE FLATMEM_36BIT;
NAME flatmem_36bit; // Same name as MODULE
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memstore_36bit_ssi.so;
INIT_FUNC memstore_36bit_init;
INIT_DONE_FUNC memstore_36bit_init_done;
QUIT_FUNC memstore_36bit_quit;
END FLATMEM_36BIT;
MODULE PSC;
NAME psc;
TYPE SHARED;
SSI_VER SSI_1.1;
DLL ../../../bin/components/tisim_psc_pv.so;
INIT_FUNC psc_init;
INIT_DONE_FUNC psc_init_done;
QUIT_FUNC psc_quit;
MODULE INTERFACES;
CONNECT1 System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_read_opin, System.C66XX_S.SHARED_SYSTEM.PSC.psc_cfg_read_ipin;
CONNECT2 System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_write_opin, System.C66XX_S.SHARED_SYSTEM.PSC.psc_cfg_write_ipin;
CONNECT3 System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_dbg_read_opin, System.C66XX_S.SHARED_SYSTEM.PSC.psc_dbg_read_ipin;
CONNECT4 System.C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_dbg_write_opin, System.C66XX_S.SHARED_SYSTEM.PSC.psc_dbg_write_ipin;
CONNECT5 System.C66XX_S.SHARED_SYSTEM.PSC.psc_reset_ipin, System.C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT6 System.C66XX_S.SHARED_SYSTEM.PSC.psc_endian_ipin, System.C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
END INTERFACES;
MODULE USER_INPUTS;
INPUT1 CPU_NAME,SHARED;
INPUT2 NUMPWRD, 32;
INPUT3 ALWAYSON, 1;
INPUT4 NUMLPSC, 16;
END USER_INPUTS;
END PSC;
MODULE MIF_TO_FUNC_PSC;
TYPE SHARED;
SSI_VER SC_1.0.0;
DLL ../../../bin/components/sim_memtr_adaptor.so;
INIT_FUNC memtr_adaptor_init;
INIT_DONE_FUNC memtr_adaptor_init_done;
QUIT_FUNC memtr_adaptor_quit;
TERMINAL MT_MIF2SSI;
END MIF_TO_FUNC_PSC;
END SHARED_SYSTEM;
END C66XX_S;
// CONNECTIONS
//CGEM_SSI connections to CPU mem_map
// CGEM program path for other
CONNECT1 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_prog_mif, C66XX_S.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT2 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_prog_mif, C66XX_S.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT3 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_prog_mif, C66XX_S.CPU_SYSTEM_2.CPU2.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT4 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_prog_mif, C66XX_S.CPU_SYSTEM_3.CPU3.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT5 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_prog_mif, C66XX_S.CPU_SYSTEM_4.CPU4.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT6 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_prog_mif, C66XX_S.CPU_SYSTEM_5.CPU5.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT7 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_prog_mif, C66XX_S.CPU_SYSTEM_6.CPU6.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
CONNECT8 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_prog_mif, C66XX_S.CPU_SYSTEM_7.CPU7.prog_mem_map, 0x0, 0xFFFFFFFF, 0;
// L1D and L1P connection for CGEM program path
CONNECT9 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x10E00000, 0x10E07FFF, 0;
CONNECT10 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x11E00000, 0x11E07FFF, 0;
CONNECT11 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2.prog_mem_map, 0x12E00000, 0x12E07FFF, 0;
CONNECT12 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3.prog_mem_map, 0x13E00000, 0x13E07FFF, 0;
CONNECT13 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4.prog_mem_map, 0x14E00000, 0x14E07FFF, 0;
CONNECT14 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5.prog_mem_map, 0x15E00000, 0x15E07FFF, 0;
CONNECT15 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6.prog_mem_map, 0x16E00000, 0x16E07FFF, 0;
CONNECT16 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7.prog_mem_map, 0x17E00000, 0x17E07FFF, 0;
CONNECT17 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x10F00000, 0x10F07FFF, 0;
CONNECT18 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x11F00000, 0x11F07FFF, 0;
CONNECT19 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2.prog_mem_map, 0x12F00000, 0x12F07FFF, 0;
CONNECT20 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3.prog_mem_map, 0x13F00000, 0x13F07FFF, 0;
CONNECT21 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4.prog_mem_map, 0x14F00000, 0x14F07FFF, 0;
CONNECT22 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5.prog_mem_map, 0x15F00000, 0x15F07FFF, 0;
CONNECT23 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6.prog_mem_map, 0x16F00000, 0x16F07FFF, 0;
CONNECT24 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7.prog_mem_map, 0x17F00000, 0x17F07FFF, 0;
CONNECT25 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_data_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT26 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_data_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT27 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_data_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT28 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_data_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT29 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_data_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT30 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_data_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT31 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_data_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0, 0xFFFFFFFF, 0;
CONNECT32 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_data_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0, 0xFFFFFFFF, 0;
// L1D and L1P connection for CGEM Data path
CONNECT33 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0x10E00000, 0x10E07FFF, 0;
CONNECT34 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0x11E00000, 0x11E07FFF, 0;
CONNECT35 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0x12E00000, 0x12E07FFF, 0;
CONNECT36 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0x13E00000, 0x13E07FFF, 0;
CONNECT37 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0x14E00000, 0x14E07FFF, 0;
CONNECT38 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0x15E00000, 0x15E07FFF, 0;
CONNECT39 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0x16E00000, 0x16E07FFF, 0;
CONNECT40 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0x17E00000, 0x17E07FFF, 0;
CONNECT41 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0x10F00000, 0x10F07FFF, 0;
CONNECT42 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0x11F00000, 0x11F07FFF, 0;
CONNECT43 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0x12F00000, 0x12F07FFF, 0;
CONNECT44 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0x13F00000, 0x13F07FFF, 0;
CONNECT45 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0x14F00000, 0x14F07FFF, 0;
CONNECT46 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0x15F00000, 0x15F07FFF, 0;
CONNECT47 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0x16F00000, 0x16F07FFF, 0;
CONNECT48 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0x17F00000, 0x17F07FFF, 0;
// Register for CGEM and XMC mapping
CONNECT49 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_reg_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT50 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_reg_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT51 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_reg_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT52 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_reg_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT53 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_reg_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT54 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_reg_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT55 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_reg_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0x01800000, 0x01BFFFFF, 0;
CONNECT56 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_reg_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0x01800000, 0x01BFFFFF, 0;
//CGEM INTSEL Connections with CPU mem_map
CONNECT57 C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT58 C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT59 C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT60 C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT61 C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT62 C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT63 C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
CONNECT64 C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELcfg_mem_mif, 0x01800000, 0x01800200, 0;
//! Connections of IDMA with CPU
CONNECT65 C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT66 C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT67 C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT68 C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT69 C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT70 C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT71 C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
CONNECT72 C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.IDMAcfg_mem_mif, 0x01820000, 0x01820114, 0;
// Register for XMC mapping
CONNECT73 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_reg_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT74 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_reg_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT75 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_reg_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT76 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_reg_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT77 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_reg_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT78 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_reg_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT79 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_reg_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0x08000000, 0x0800FFFF, 0;
CONNECT80 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_reg_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0x08000000, 0x0800FFFF, 0;
//! Connections of IDMA with CGEM_SSI
CONNECT81 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.idma_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT82 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.idma_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT83 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.idma_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT84 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.idma_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT85 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.idma_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT86 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.idma_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT87 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.idma_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
CONNECT88 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.idma_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_data_mif, 0x00000000, 0xFFFFFFFF, 0;
// L1D and L1P connection forIDMA
CONNECT89 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT90 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT91 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT92 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT93 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT94 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT95 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT96 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.idma_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT97 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT98 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT99 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT100 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT101 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT102 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT103 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT104 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.idma_mem_map, 0x00F00000, 0x00F07FFF, 0;
//MSMC connections with CGEM SSI
CONNECT105 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_read_output_opin;
CONNECT106 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_write_output_opin;
CONNECT107 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_dbg_read_output_opin;
CONNECT108 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM0_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_dbg_write_output_opin;
CONNECT109 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_read_output_opin;
CONNECT110 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_write_output_opin;
CONNECT111 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_dbg_read_output_opin;
CONNECT112 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM1_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_dbg_write_output_opin;
CONNECT113 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM2_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_memtr_read_output_opin;
CONNECT114 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM2_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_memtr_write_output_opin;
CONNECT115 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM2_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_memtr_dbg_read_output_opin;
CONNECT116 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM2_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_memtr_dbg_write_output_opin;
CONNECT117 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM3_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_memtr_read_output_opin;
CONNECT118 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM3_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_memtr_write_output_opin;
CONNECT119 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM3_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_memtr_dbg_read_output_opin;
CONNECT120 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM3_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_memtr_dbg_write_output_opin;
CONNECT121 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM4_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_memtr_read_output_opin;
CONNECT122 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM4_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_memtr_write_output_opin;
CONNECT123 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM4_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_memtr_dbg_read_output_opin;
CONNECT124 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM4_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_memtr_dbg_write_output_opin;
CONNECT125 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM5_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_memtr_read_output_opin;
CONNECT126 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM5_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_memtr_write_output_opin;
CONNECT127 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM5_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_memtr_dbg_read_output_opin;
CONNECT128 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM5_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_memtr_dbg_write_output_opin;
CONNECT129 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM6_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_memtr_read_output_opin;
CONNECT130 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM6_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_memtr_write_output_opin;
CONNECT131 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM6_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_memtr_dbg_read_output_opin;
CONNECT132 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM6_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_memtr_dbg_write_output_opin;
CONNECT133 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM7_memtr_read_input_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_memtr_read_output_opin;
CONNECT134 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM7_memtr_write_input_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_memtr_write_output_opin;
CONNECT135 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM7_memtr_dbg_read_input_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_memtr_dbg_read_output_opin;
CONNECT136 C66XX_S.SHARED_SYSTEM.MSMC.msmc_cGEM7_memtr_dbg_write_input_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_memtr_dbg_write_output_opin;
//32BIT mif connection with MSMC mem_map
CONNECT137 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
//TIMER_64 connections with MSMC mem_map
CONNECT138 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_0_mif, 0x02200000, 0x0220007F, -0x02200000;
CONNECT139 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_1_mif, 0x02210000, 0x0221007F, -0x02210000;
CONNECT140 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_2_mif, 0x02220000, 0x0222007F, -0x02220000;
CONNECT141 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_3_mif, 0x02230000, 0x0223007F, -0x02230000;
CONNECT142 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_4_mif, 0x02240000, 0x0224007F, -0x02240000;
CONNECT143 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_5_mif, 0x02250000, 0x0225007F, -0x02250000;
CONNECT144 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_6_mif, 0x02260000, 0x0226007F, -0x02260000;
CONNECT145 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_7_mif, 0x02270000, 0x0227007F, -0x02270000;
CONNECT146 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_8_mif, 0x02280000, 0x0228007F, -0x02280000;
CONNECT147 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_9_mif, 0x02290000, 0x0229007F, -0x02290000;
CONNECT148 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_10_mif, 0x022A0000, 0x022A007F, -0x022A0000;
CONNECT149 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_11_mif, 0x022B0000, 0x022B007F, -0x022B0000;
CONNECT150 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_12_mif, 0x022C0000, 0x022C007F, -0x022C0000;
CONNECT151 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_13_mif, 0x022D0000, 0x022D007F, -0x022D0000;
CONNECT152 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_14_mif, 0x022E0000, 0x022E007F, -0x022E0000;
CONNECT153 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_15_mif, 0x022F0000, 0x022F007F, -0x022F0000;
//EDMA connections with MSMC mem_map
CONNECT154 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02700000, 0x02707FFF, 0;
//! Decide whether to use memtr adaptors for TPTC accesses
//CONNECT35 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02760000, 0x027603FF, 0;
//CONNECT36 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02768000, 0x027683FF, 0;
CONNECT155 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02720000, 0x02727FFF, 0;
CONNECT156 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x02740000, 0x02747FFF, 0;
// CP_INTC connections with MSMC mem_map
CONNECT157 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_mif_opin, 0x02600000, 0x02601FFF, -0x02600000;
CONNECT158 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_mif_opin, 0x02604000, 0x02605FFF, -0x02604000;
CONNECT159 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_mif_opin, 0x02608000, 0x02609FFF, -0x02608000;
CONNECT160 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_mif_opin, 0x0260C000, 0x0260DFFF, -0x0260C000;
// DDR3(to FLATMEM_36BIT) connections with MSMC mem_map
CONNECT161 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0x21000000, 0x210000FF, 0; //EMIF
CONNECT162 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0x80000000, 0xFFFFFFFF, 0; //DDR
//SEMAPHORE connections with MEMTRs
CONNECT163 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_cfg_read_ipin;
CONNECT164 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_cfg_write_ipin;
CONNECT165 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_dbg_read_ipin;
CONNECT166 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_dbg_write_ipin;
//VBUSM CMD packet
CONNECT167 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_memtr_vbusm_cmd_output_opin;
CONNECT168 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_memtr_vbusm_cmd_output_opin;
CONNECT169 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_memtr_vbusm_cmd_output_opin;
CONNECT170 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_memtr_vbusm_cmd_output_opin;
CONNECT171 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_memtr_vbusm_cmd_output_opin;
CONNECT172 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_memtr_vbusm_cmd_output_opin;
CONNECT173 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_memtr_vbusm_cmd_output_opin;
CONNECT174 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.vbusm_cmd_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_memtr_vbusm_cmd_output_opin;
// SEMAPHORE connections to with MSMC mem_map
CONNECT175 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_mif_opin, 0x02640000, 0x026407FF, 0;
//IPC connections with MSMC mem_map
CONNECT176 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620200, 0x0262029F, -0x02620200;
//GPIO connection with MSMC mem_map
CONNECT177 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02320000, 0x023200FF, -0x02320000;
//QM connections with MEMTRs
//QM Config
CONNECT178 C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_cfg_read_ipin;
CONNECT179 C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_cfg_write_ipin;
CONNECT180 C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dbg_read_ipin;
CONNECT181 C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dbg_write_ipin;
//QM PDSP Scratch RAM (PDSP Command I/F):
CONNECT182 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_read_ipin;
CONNECT183 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_write_ipin;
CONNECT184 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_dbg_read_ipin;
CONNECT185 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_cmd_dbg_write_ipin;
//QMSS PDSP Master
CONNECT186 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_read_ipin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_master_read_opin;
CONNECT187 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_write_ipin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_pdsp_master_write_opin;
//QM connections with MSMC mem_map
CONNECT188 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A00000, 0x02AABFFF, -0x02A00000;
CONNECT189 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02ab8000, 0x02abdFFF, -0x02A00000;
// CONNECT194 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02AB8000, 0x02AB8FFF, -0x02A00000;
//CDMA_INFRA connections with MEMTRs
//CDMA_INFRA Config
CONNECT190 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_cfg_read_ipin;
CONNECT191 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_cfg_write_ipin;
CONNECT192 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_dbg_read_ipin;
CONNECT193 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_dbg_write_ipin;
//CDMA_INFRA Master
CONNECT194 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_read_ipin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_mstr_read_opin;
CONNECT195 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_write_ipin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_mstr_write_opin;
//CDMA_INFRA connections with MSMC mem_map
CONNECT196 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A6C000, 0x02A6DFFF, -0x02A00000;
//SRIO connections with MSMC mem_map
CONNECT197 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02900000, 0x02900FFF, 0;
CONNECT198 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_mif_opin, 0x50000000, 0x5FFFFFFF, 0;
//CDMA_SRIO connections with MSMC mem_map
CONNECT199 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02901000, 0x02920FFF, -0x02900000;
CONNECT200 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0x0290B000, 0x0291BE4C, 0; //<CHECK>
//! PA Sub-system connections
// Switchss connection to PA (packet interface)
CONNECT201 C66XX_S.SHARED_SYSTEM.PASS.pass_sgmii_rx1_ipin, C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_tstrm_tx1_data_opin;
CONNECT202 C66XX_S.SHARED_SYSTEM.PASS.pass_sgmii_rx2_ipin, C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_tstrm_tx2_data_opin;
CONNECT203 C66XX_S.SHARED_SYSTEM.PASS.pass_sgmii_tx_data_opin, C66XX_S.SHARED_SYSTEM.SWITCHSS.switchss_tstrm_rx_data_ipin;
//SWITCHSS connections with MSMC mem_map
CONNECT204 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02090000, 0x0209FFFF, -0x02090000; //actual end-0x02090FFF, giving relative address
//SWITCHSS connections with MSMC mem_map
CONNECT205 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620340, 0x02620357, -0x02620000; //actual end-0x02090FFF, giving relative address<CHECK>
//PASS connections with MSMC mem_map
CONNECT206 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02000000, 0x02003FFF, -0x02000000;
CONNECT207 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02006000, 0x0207FFFF, -0x02000000;
//CDMA_PASS connections with MSMC mem_map
CONNECT208 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02004000, 0x02005FFF, -0x02000000;
// PCIE connection with MSMC mem_map
CONNECT209 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_mif_opin, 0x21800000, 0x21807FFF, 0; //MMR region
//FLATMEM_36BIT connections with MSMC
CONNECT210 C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_read_input_ipin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_read_output_opin;
CONNECT211 C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_write_input_ipin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_write_output_opin;
CONNECT212 C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_dbg_read_input_ipin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_dbg_read_output_opin;
CONNECT213 C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_dbg_write_input_ipin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_EMIF_memtr_dbg_write_output_opin;
//MEMTR connections to SMS and SES interfaces of MSMC
//SMS connections
CONNECT214 C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_read_input_ipin;
CONNECT215 C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_write_input_ipin;
CONNECT216 C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_dbg_read_input_ipin;
CONNECT217 C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SMS_memtr_dbg_write_input_ipin;
//SES connections
CONNECT218 C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SES_memtr_read_input_ipin;
CONNECT219 C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SES_memtr_write_input_ipin;
CONNECT220 C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SES_memtr_dbg_read_input_ipin;
CONNECT221 C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.MSMC.msmc_SES_memtr_dbg_write_input_ipin;
//EDMA Memory map Connections
//32BIT mif connections with EDMA mem_map
CONNECT222 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
CONNECT223 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
CONNECT224 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
//TIMER_64 connections with EDMA mem_map
CONNECT225 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_0_mif, 0x02200000, 0x0220007F, -0x02200000;
CONNECT226 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_1_mif, 0x02210000, 0x0221007F, -0x02210000;
CONNECT227 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_2_mif, 0x02220000, 0x0222007F, -0x02220000;
CONNECT228 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_3_mif, 0x02230000, 0x0223007F, -0x02230000;
CONNECT229 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_4_mif, 0x02240000, 0x0224007F, -0x02240000;
CONNECT230 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_5_mif, 0x02250000, 0x0225007F, -0x02250000;
CONNECT231 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_6_mif, 0x02260000, 0x0226007F, -0x02260000;
CONNECT232 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_7_mif, 0x02270000, 0x0227007F, -0x02270000;
CONNECT233 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_8_mif, 0x02280000, 0x0228007F, -0x02280000;
CONNECT234 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_9_mif, 0x02290000, 0x0229007F, -0x02290000;
CONNECT235 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_10_mif, 0x022A0000, 0x022A007F, -0x022A0000;
CONNECT236 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_11_mif, 0x022B0000, 0x022B007F, -0x022B0000;
CONNECT237 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_12_mif, 0x022C0000, 0x022C007F, -0x022C0000;
CONNECT238 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_13_mif, 0x022D0000, 0x022D007F, -0x022D0000;
CONNECT239 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_14_mif, 0x022E0000, 0x022E007F, -0x022E0000;
CONNECT240 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_15_mif, 0x022F0000, 0x022F007F, -0x022F0000;
CONNECT241 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_0_mif, 0x02200000, 0x0220007F, -0x02200000;
CONNECT242 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_1_mif, 0x02210000, 0x0221007F, -0x02210000;
CONNECT243 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_2_mif, 0x02220000, 0x0222007F, -0x02220000;
CONNECT244 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_3_mif, 0x02230000, 0x0223007F, -0x02230000;
CONNECT245 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_4_mif, 0x02240000, 0x0224007F, -0x02240000;
CONNECT246 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_5_mif, 0x02250000, 0x0225007F, -0x02250000;
CONNECT247 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_6_mif, 0x02260000, 0x0226007F, -0x02260000;
CONNECT248 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_7_mif, 0x02270000, 0x0227007F, -0x02270000;
CONNECT249 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_8_mif, 0x02280000, 0x0228007F, -0x02280000;
CONNECT250 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_9_mif, 0x02290000, 0x0229007F, -0x02290000;
CONNECT251 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_10_mif, 0x022A0000, 0x022A007F, -0x022A0000;
CONNECT252 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_11_mif, 0x022B0000, 0x022B007F, -0x022B0000;
CONNECT253 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_12_mif, 0x022C0000, 0x022C007F, -0x022C0000;
CONNECT254 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_13_mif, 0x022D0000, 0x022D007F, -0x022D0000;
CONNECT255 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_14_mif, 0x022E0000, 0x022E007F, -0x022E0000;
CONNECT256 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_15_mif, 0x022F0000, 0x022F007F, -0x022F0000;
CONNECT257 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_0_mif, 0x02200000, 0x0220007F, -0x02200000;
CONNECT258 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_1_mif, 0x02210000, 0x0221007F, -0x02210000;
CONNECT259 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_2_mif, 0x02220000, 0x0222007F, -0x02220000;
CONNECT260 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_3_mif, 0x02230000, 0x0223007F, -0x02230000;
CONNECT261 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_4_mif, 0x02240000, 0x0224007F, -0x02240000;
CONNECT262 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_5_mif, 0x02250000, 0x0225007F, -0x02250000;
CONNECT263 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_6_mif, 0x02260000, 0x0226007F, -0x02260000;
CONNECT264 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_7_mif, 0x02270000, 0x0227007F, -0x02270000;
CONNECT265 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_8_mif, 0x02280000, 0x0228007F, -0x02280000;
CONNECT266 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_9_mif, 0x02290000, 0x0229007F, -0x02290000;
CONNECT267 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_10_mif, 0x022A0000, 0x022A007F, -0x022A0000;
CONNECT268 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_11_mif, 0x022B0000, 0x022B007F, -0x022B0000;
CONNECT269 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_12_mif, 0x022C0000, 0x022C007F, -0x022C0000;
CONNECT270 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_13_mif, 0x022D0000, 0x022D007F, -0x022D0000;
CONNECT271 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_14_mif, 0x022E0000, 0x022E007F, -0x022E0000;
CONNECT272 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.TIMER64_15_mif, 0x022F0000, 0x022F007F, -0x022F0000;
//EDMA connections with other EDMA mem_map
CONNECT273 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02720000, 0x02727FFF, 0;
// CONNECT207 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02770000, 0x027703FF, 0;
// CONNECT208 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02778000, 0x027783FF, 0;
// CONNECT209 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02780000, 0x027803FF, 0;
// CONNECT210 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02788000, 0x027883FF, 0;
CONNECT274 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x02740000, 0x02747FFF, 0;
// CONNECT212 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x02790000, 0x027903FF, 0;
// CONNECT213 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x02798000, 0x027983FF, 0;
// CONNECT214 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x027A0000, 0x027A03FF, 0;
// CONNECT215 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x027A8000, 0x027A83FF, 0;
CONNECT275 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02700000, 0x02707FFF, 0;
CONNECT276 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x02740000, 0x02747FFF, 0;
CONNECT277 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02700000, 0x02707FFF, 0;
CONNECT278 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02720000, 0x02727FFF, 0;
//! EDMA connections with itself
//! All the EDMA read/write ports are fully connected with all the EDMA抯 registers.
//! EDMA X can read/write EDMA Y抯 register. X and Y can be the same or they can be different.
CONNECT279 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02700000, 0x02707FFF, 0;
// CONNECT1341 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02760000, 0x027603FF, 0;
// CONNECT1342 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_0_mif, 0x02768000, 0x027683FF, 0;
CONNECT280 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_1_mif, 0x02720000, 0x02727FFF, 0;
CONNECT281 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.EDMA_2_mif, 0x02740000, 0x02747FFF, 0;
// CP_INTC connections with EDMA mem_map
CONNECT282 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_mif_opin, 0x02600000, 0x02601FFF, -0x02600000;
CONNECT283 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_mif_opin, 0x02604000, 0x02605FFF, -0x02604000;
CONNECT284 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_mif_opin, 0x02608000, 0x02609FFF, -0x02608000;
CONNECT285 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_mif_opin, 0x0260C000, 0x0260DFFF, -0x0260C000;
CONNECT286 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_mif_opin, 0x02600000, 0x02601FFF, -0x02600000;
CONNECT287 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_mif_opin, 0x02604000, 0x02605FFF, -0x02604000;
CONNECT288 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_mif_opin, 0x02608000, 0x02609FFF, -0x02608000;
CONNECT289 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_mif_opin, 0x0260C000, 0x0260DFFF, -0x0260C000;
CONNECT290 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_mif_opin, 0x02600000, 0x02601FFF, -0x02600000;
CONNECT291 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_mif_opin, 0x02604000, 0x02605FFF, -0x02604000;
CONNECT292 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_mif_opin, 0x02608000, 0x02609FFF, -0x02608000;
CONNECT293 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_mif_opin, 0x0260C000, 0x0260DFFF, -0x0260C000;
// L1/L2 MEM connections connections with EDMA mem map
CONNECT294 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT295 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT296 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT297 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT298 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT299 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT300 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT301 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT302 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT303 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT304 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT305 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT306 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT307 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT308 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT309 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT310 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT311 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT312 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT313 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT314 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT315 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT316 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT317 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// L1/L2 MEM connections connections with EDMA mem map
CONNECT318 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT319 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT320 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT321 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT322 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT323 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT324 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT325 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT326 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT327 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT328 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT329 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT330 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT331 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT332 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT333 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT334 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT335 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT336 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT337 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT338 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT339 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT340 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT341 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// L1/L2 MEM connections with EDMA mem map
CONNECT342 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT343 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT344 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT345 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT346 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT347 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT348 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT349 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT350 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT351 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT352 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT353 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT354 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT355 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT356 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT357 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT358 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT359 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT360 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT361 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT362 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT363 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT364 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT365 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// SEMAPHORE connections to with EDMA mem_map( through MEMTR)
CONNECT366 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_mif_opin, 0x02640000, 0x026407FF, 0;
CONNECT367 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_mif_opin, 0x02640000, 0x026407FF, 0;
CONNECT368 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_mif_opin, 0x02640000, 0x026407FF, 0;
//IPC connections with EDMA mem_map
CONNECT369 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620200, 0x0262029F, -0x02620200;
CONNECT370 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620200, 0x0262029F, -0x02620200;
CONNECT371 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620200, 0x0262029F, -0x02620200;
// GPIO connections with EDMA mem_map( through MIF_TO_FUNC)
CONNECT372 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02320000, 0x023200FF, -0x02320000;
CONNECT373 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02320000, 0x023200FF, -0x02320000;
CONNECT374 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02320000, 0x023200FF, -0x02320000;
// QM connections with EDMA mem_map( through MEMTR)
CONNECT375 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_mif_opin, 0x02a00000, 0x02AABFFF, -0x02A00000;
CONNECT376 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02ab8000, 0x02abdFFF, -0x02A00000;
// CONNECT440 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02FFFFFF, 0x02FFFFFF, -0x02A00000; //not used!
CONNECT377 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A00000, 0x02AABFFF, -0x02A00000;
CONNECT378 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02AB8000, 0x02ABDFFF, -0x02A00000;
// CONNECT443 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02FFFFFF, 0x02FFFFFF, -0x02A00000; //not used!
CONNECT379 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A00000, 0x02AABFFF, -0x02A00000;
CONNECT380 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02ab8000, 0x02abdFFF, -0x02A00000;
// CONNECT446 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02FFFFFF, 0x02FFFFFF, -0x02A00000; //not used!
//CDMA_INFRA connections with EDMA mem_map( through MEMTR)
CONNECT381 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A6C000, 0x02A6DFFF, -0x02A00000;
CONNECT382 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A6C000, 0x02A6DFFF, -0x02A00000;
CONNECT383 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_mif_opin, 0x02A6C000, 0x02A6DFFF, -0x02A00000;
//SRIO connections with EDMA mem_map
CONNECT384 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02900000, 0x02900FFF, 0;
CONNECT385 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_mif_opin, 0x50000000, 0x5FFFFFFF, 0;
CONNECT386 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02900000, 0x02900FFF, 0;
CONNECT387 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_mif_opin, 0x50000000, 0x5FFFFFFF, 0;
CONNECT388 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02900000, 0x02900FFF, 0;
CONNECT389 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_mif_opin, 0x50000000, 0x5FFFFFFF, 0;
//CDMA_SRIO connections with EDMA mem_map
CONNECT390 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02901000, 0x02920FFF, -0x02900000;
CONNECT391 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02901000, 0x02920FFF, -0x02900000;
CONNECT392 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_mif_opin, 0x02901000, 0x02920FFF, -0x02900000;
//SRIO TUNDRA
CONNECT393 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0x0290B000, 0x0291BE4C, 0; //<CHECK>
CONNECT394 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0x0290B000, 0x0291BE4C, 0; //<CHECK>
CONNECT395 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0x0290B000, 0x0291BE4C, 0; //<CHECK>
//! PA Sub-system connections
//SWITCHSS connections with EDMA mem_map
CONNECT396 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02090000, 0x0209FFFF, -0x02090000; //actual end-0x02090FFF, giving relative address
CONNECT397 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02090000, 0x0209FFFF, -0x02090000; //actual end-0x02090FFF, giving relative address
CONNECT398 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02090000, 0x0209FFFF, -0x02090000; //actual end-0x02090FFF, giving relative address
//SWITCHSS SERDES connections with EDMA mem_map
CONNECT399 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620340, 0x02620357, -0x02620000; //actual end-0x02090FFF, giving relative address
CONNECT400 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620340, 0x02620357, -0x02620000; //actual end-0x02090FFF, giving relative address
CONNECT401 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_mif_opin, 0x02620340, 0x02620357, -0x02620000; //actual end-0x02090FFF, giving relative address
//PASS connections with EDMA mem_map
CONNECT402 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02000000, 0x02003FFF, -0x02000000;
CONNECT403 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02006000, 0x0207FFFF, -0x02000000;
CONNECT404 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02000000, 0x02003FFF, -0x02000000;
CONNECT405 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02006000, 0x0207FFFF, -0x02000000;
CONNECT406 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02000000, 0x02003FFF, -0x02000000;
CONNECT407 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x02006000, 0x0207FFFF, -0x02000000;
//CDMA_PASS connections with EDMA mem_map
CONNECT408 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02004000, 0x02005FFF, -0x02000000;
CONNECT409 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02004000, 0x02005FFF, -0x02000000;
CONNECT410 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_mif_opin, 0x02004000, 0x02005FFF, -0x02000000;
// PCIE connection with EDMA mem_map
CONNECT411 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_mif_opin, 0x21800000, 0x21807FFF, 0; //MMR region
CONNECT412 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_mif_opin, 0x21800000, 0x21807FFF, 0; //MMR region
CONNECT413 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_mif_opin, 0x21800000, 0x21807FFF, 0; //MMR region
// SMS and SES MEMTR connections with EDMA mem_map
//SMS connections
CONNECT414 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT415 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
CONNECT416 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT417 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
CONNECT418 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT419 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
//SES connections(DDR connections)
CONNECT420 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0;//EMIF
CONNECT421 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0;//DDR
CONNECT422 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0;//EMIF
CONNECT423 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0;//DDR
CONNECT424 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0;//EMIF
CONNECT425 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0;//DDR
//QM_Accumulator Memory Map connections
// 32BIT mif connections with QM_Accumulator Master mem_map
CONNECT426 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
// L1/L2 MEM connections with QM_Accumulator Master mem_map
CONNECT427 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT428 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT429 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT430 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT431 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT432 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT433 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT434 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT435 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT436 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT437 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT438 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT439 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT440 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT441 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT442 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT443 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT444 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT445 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT446 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT447 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT448 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT449 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT450 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// SMS and SES MEMTR connections with QM_Accumulator Master mem_map
//SMS connections
CONNECT451 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT452 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
//SES connections(DDR connections)
CONNECT453 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0; //EMIF
CONNECT454 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0; //DDR
//PASS Memory Map connections
// 32BIT mif connections with PASS Master mem_map
CONNECT455 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
// L1/L2 connections with PASS Master mem_map
CONNECT456 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT457 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT458 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT459 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT460 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT461 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT462 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT463 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT464 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT465 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT466 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT467 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT468 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT469 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT470 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT471 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT472 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT473 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT474 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT475 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT476 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT477 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT478 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT479 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// SMS and SES MEMTR connections with PASS Master mem_map
//SMS connections
CONNECT480 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT481 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
//SES connections(DDR connections)
CONNECT482 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0; //EMIF
CONNECT483 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0; //DDR
//CDMA_INFRA Master Memory Map connections
// 32BIT mif connections with CDMA_INFRA Master mem_map
CONNECT484 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
// L1/L2 connections with CDMA_INFRA Master mem_map
CONNECT485 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT486 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT487 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT488 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT489 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT490 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT491 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT492 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT493 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT494 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT495 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT496 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT497 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT498 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT499 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT500 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT501 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT502 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT503 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT504 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT505 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT506 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT507 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT508 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// SMS and SES MEMTR connections with CDMA_INFRA Master mem_map
//SMS connections
CONNECT509 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT510 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
//SES connections(DDR connections)
CONNECT511 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0; //EMIF
CONNECT512 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0; //DDR
// QM_Config connections with CDMA_INFRA Master mem_map
CONNECT513 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT514 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02AB8000, 0x02ABDFFF, -0x02A00000;
// CONNECT599 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02FFFFFF, 0x02FFFFFF, -0x02A00000; //not used!
//CDMA_SRIO Master Memory Map connections
// 32BIT mif connections with CDMA_SRIO Master mem_map
CONNECT515 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
// L1/L2 connections with CDMA_SRIO Master mem_map
CONNECT516 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT517 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT518 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT519 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT520 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT521 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT522 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT523 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT524 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT525 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT526 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT527 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT528 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT529 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT530 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT531 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT532 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT533 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT534 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT535 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT536 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT537 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT538 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT539 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// SMS and SES MEMTR connections with CDMA_SRIO Master mem_map
//SMS connections
CONNECT540 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT541 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
//SES connections(DDR connections)
CONNECT542 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0; //EMIF
CONNECT543 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0; //DDR
// QM_Config connections with CDMA_SRIO Master mem_map
CONNECT544 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT545 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02AB8000, 0x02ABDFFF, -0x02A00000;
// CONNECT619 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02FFFFFF, 0x02FFFFFF, -0x02A00000; //not used!
//CDMA_PASS Master Memory Map connections
// 32BIT mif connections with CDMA_PASS Master mem_map
CONNECT546 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_mif, 0, 0xFFFFFFFF, 0;
// L1/L2 connections with CDMA_PASS Master mem_map
CONNECT547 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT548 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT549 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT550 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT551 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT552 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT553 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT554 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT555 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT556 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT557 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT558 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT559 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT560 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT561 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT562 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT563 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT564 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT565 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT566 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT567 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT568 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT569 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT570 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// SMS and SES MEMTR connections with CDMA_PASS Master mem_map
//SMS connections
CONNECT571 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0BC00000, 0x0BCFFFFF, 0; //MSMC Config
CONNECT572 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_mif_opin, 0x0C000000, 0x0C3FFFFF, 0; //MSMC RAM
//SES connections(DDR connections)
CONNECT573 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x21000000, 0x210000FF, 0; //EMIF
CONNECT574 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_mif_opin, 0x80000000, 0xFFFFFFFF, 0; //DDR
// QM_Config connections with CDMA_PASS Master mem_map
CONNECT575 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT576 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_mif_opin, 0x02AB8000, 0x02ABDFFF, -0x02A00000;
// CONNECT1636 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_mmap_ipin, C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_mif_opin, 0x02FFFFFF, 0x02FFFFFF, -0x02A00000; //not used!
//RESET Connections
CONNECT577 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_RESET;
CONNECT578 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_1.CPU1_RESET;
CONNECT579 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_2.CPU2_RESET;
CONNECT580 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_3.CPU3_RESET;
CONNECT581 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_4.CPU4_RESET;
CONNECT582 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_5.CPU5_RESET;
CONNECT583 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_6.CPU6_RESET;
CONNECT584 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_reset_ipin, C66XX_S.CPU_SYSTEM_7.CPU7_RESET;
CONNECT585 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_in;
CONNECT586 C66XX_S.SHARED_SYSTEM.MSMC.msmc_reset_ipin, System.SimBridge.global_reset_list;
CONNECT587 C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_reset_ipin, System.SimBridge.global_reset_list;
CONNECT588 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_0.reset;
CONNECT589 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_1.reset;
CONNECT590 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_2.reset;
CONNECT591 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_3.reset;
CONNECT592 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_4.reset;
CONNECT593 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_5.reset;
CONNECT594 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_6.reset;
CONNECT595 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_7.reset;
CONNECT596 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_8.reset;
CONNECT597 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_9.reset;
CONNECT598 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_10.reset;
CONNECT599 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_11.reset;
CONNECT600 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_12.reset;
CONNECT601 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_13.reset;
CONNECT602 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_14.reset;
CONNECT603 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.TIMER64_15.reset;
CONNECT604 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.EDMA_0.reset;
CONNECT605 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.EDMA_1.reset;
CONNECT606 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.EDMA_2.reset;
CONNECT607 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_reset_in, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT608 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_reset_in, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT609 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_reset_in, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT610 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_reset_in, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT611 C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_reset_ipin, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT612 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_reset_ipin, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT613 C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_reset_ipin, C66XX_S.SHARED_SYSTEM.SHARED_SYSTEM_INTF.reset_out;
CONNECT614 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.IPC.reset;
CONNECT615 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.memtr_reset_ipin;
CONNECT616 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.BOOT_ROM.reset;
CONNECT617 C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT618 C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT619 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT620 C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT621 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
// CONNECT633 C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT622 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT623 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT624 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT625 C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT626 C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT627 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT628 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT629 C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT630 C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT631 C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT632 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT633 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT634 C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
//Endianess Connections
CONNECT635 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT636 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_1.CPU1_endianness;
CONNECT637 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_2.CPU2_endianness;
CONNECT638 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_3.CPU3_endianness;
CONNECT639 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_4.CPU4_endianness;
CONNECT640 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_5.CPU5_endianness;
CONNECT641 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_6.CPU6_endianness;
CONNECT642 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_endian_ipin, C66XX_S.CPU_SYSTEM_7.CPU7_endianness;
//! since the whole system is of the same endianness, connecting any CPU's endian to the entire shared Components
CONNECT643 C66XX_S.SHARED_SYSTEM.MSMC.msmc_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT644 C66XX_S.SHARED_SYSTEM.FLATMEM_36BIT.mem36_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT645 C66XX_S.SHARED_SYSTEM.TIMER64_0.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT646 C66XX_S.SHARED_SYSTEM.TIMER64_1.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT647 C66XX_S.SHARED_SYSTEM.TIMER64_2.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT648 C66XX_S.SHARED_SYSTEM.TIMER64_3.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT649 C66XX_S.SHARED_SYSTEM.TIMER64_4.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT650 C66XX_S.SHARED_SYSTEM.TIMER64_5.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT651 C66XX_S.SHARED_SYSTEM.TIMER64_6.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT652 C66XX_S.SHARED_SYSTEM.TIMER64_7.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT653 C66XX_S.SHARED_SYSTEM.TIMER64_8.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT654 C66XX_S.SHARED_SYSTEM.TIMER64_9.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT655 C66XX_S.SHARED_SYSTEM.TIMER64_10.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT656 C66XX_S.SHARED_SYSTEM.TIMER64_11.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT657 C66XX_S.SHARED_SYSTEM.TIMER64_12.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT658 C66XX_S.SHARED_SYSTEM.TIMER64_13.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT659 C66XX_S.SHARED_SYSTEM.TIMER64_14.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT660 C66XX_S.SHARED_SYSTEM.TIMER64_15.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT661 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_endian_in, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT662 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_endian_in, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT663 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_endian_in, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT664 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_endian_in, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT665 C66XX_S.CPU_SYSTEM_0.CPU0_endianness, C66XX_S.SHARED_SYSTEM.EDMA_0.endian_in;
CONNECT666 C66XX_S.CPU_SYSTEM_0.CPU0_endianness, C66XX_S.SHARED_SYSTEM.EDMA_1.endian_in;
CONNECT667 C66XX_S.CPU_SYSTEM_0.CPU0_endianness, C66XX_S.SHARED_SYSTEM.EDMA_2.endian_in;
CONNECT668 C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT669 C66XX_S.SHARED_SYSTEM.IPC.endian, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT670 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian; //Big-endian
CONNECT671 C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness_big_endian; //Big-endian
CONNECT672 C66XX_S.SHARED_SYSTEM.BOOT_ROM.endian_in, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT673 C66XX_S.SHARED_SYSTEM.MEMTR_GPIO_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
//! MEMTR adaptors endianess
CONNECT674 C66XX_S.SHARED_SYSTEM.MEMTR_SMS.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT675 C66XX_S.SHARED_SYSTEM.MEMTR_SES.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT676 C66XX_S.SHARED_SYSTEM.MEMTR_SEMAPHORE_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT677 C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT678 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Command.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
// CONNECT691 C66XX_S.SHARED_SYSTEM.MEMTR_QM_High_Accumulator.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT679 C66XX_S.SHARED_SYSTEM.MEMTR_QM_PDSP_Master.MT_SSI2MMAP.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT680 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT681 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_INFRA_Master.MT_SSI2MMAP.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT682 C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT683 C66XX_S.SHARED_SYSTEM.MEMTR_SRIO_Slave.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT684 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT685 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_SRIO_Master.MT_SSI2MMAP.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT686 C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT687 C66XX_S.SHARED_SYSTEM.MEMTR_SWITCHSS_SERDES_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT688 C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT689 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT690 C66XX_S.SHARED_SYSTEM.MEMTR_CDMA_PASS_Master.MT_SSI2MMAP.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT691 C66XX_S.SHARED_SYSTEM.MEMTR_PCIE_Slave.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
//! CDMA_INFRA connections
//! These pins setup loopback mode for the Streaming I/f
CONNECT692 C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_thread_mready_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_thread_mready_ipin;
CONNECT693 C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_thread_sready_ipin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_thread_sready_opin;
CONNECT694 C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_data_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_data_ipin;
CONNECT695 C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_tstrm_data_accept_ipin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_rstrm_data_accept_opin;
CONNECT696 System.C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_rx_teardown_req_opin, System.C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_rx_teardown_ack_ipin;
//! QUEUE_MANAGER with CDMA_INFRA
CONNECT697 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_qmgr_que_pend1_opin, C66XX_S.SHARED_SYSTEM.CDMA_INFRA.cdma_que_pend_ipin;
//! QUEUE_MANAGER with CDMA_SRIO
CONNECT698 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_qmgr_que_pend4_opin, C66XX_S.SHARED_SYSTEM.CDMA_SRIO.cdma_que_pend_ipin;
//! QUEUE_MANAGER with CDMA_PASS
CONNECT699 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_qmgr_que_pend3_opin, C66XX_S.SHARED_SYSTEM.CDMA_PASS.cdma_que_pend_ipin;
//****************************************************************************************************************************//
//! NMI connections from IPC
CONNECT700 C66XX_S.CPU_SYSTEM_0.CPU0.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_0;
CONNECT701 C66XX_S.CPU_SYSTEM_1.CPU1.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_1;
CONNECT702 C66XX_S.CPU_SYSTEM_2.CPU2.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_2;
CONNECT703 C66XX_S.CPU_SYSTEM_3.CPU3.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_3;
CONNECT704 C66XX_S.CPU_SYSTEM_4.CPU4.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_4;
CONNECT705 C66XX_S.CPU_SYSTEM_5.CPU5.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_5;
CONNECT706 C66XX_S.CPU_SYSTEM_6.CPU6.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_6;
CONNECT707 C66XX_S.CPU_SYSTEM_7.CPU7.NMI, C66XX_S.SHARED_SYSTEM.IPC_cpu_nmi_7;
//****************************************************************************************************************************//
//! Exposing CPU boundary Pins to Pin-connect Plugin
CONNECT708 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.NMI, CPU0_NMI;
CONNECT709 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.NMI, CPU1_NMI;
CONNECT710 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.NMI, CPU2_NMI;
CONNECT711 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.NMI, CPU3_NMI;
CONNECT712 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.NMI, CPU4_NMI;
CONNECT713 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.NMI, CPU5_NMI;
CONNECT714 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.NMI, CPU6_NMI;
CONNECT715 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.NMI, CPU7_NMI;
CONNECT716 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT4, CPU0_INT4;
CONNECT717 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT5, CPU0_INT5;
CONNECT718 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT6, CPU0_INT6;
CONNECT719 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT7, CPU0_INT7;
CONNECT720 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT8, CPU0_INT8;
CONNECT721 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT9, CPU0_INT9;
CONNECT722 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT10, CPU0_INT10;
CONNECT723 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT11, CPU0_INT11;
CONNECT724 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT12, CPU0_INT12;
CONNECT725 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT13, CPU0_INT13;
CONNECT726 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT14, CPU0_INT14;
CONNECT727 C66XX_S.CPU_SYSTEM_0.CPU0.PINC, C66XX_S.CPU_SYSTEM_0.CPU0.INT15, CPU0_INT15;
CONNECT728 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT4, CPU1_INT4;
CONNECT729 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT5, CPU1_INT5;
CONNECT730 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT6, CPU1_INT6;
CONNECT731 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT7, CPU1_INT7;
CONNECT732 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT8, CPU1_INT8;
CONNECT733 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT9, CPU1_INT9;
CONNECT734 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT10, CPU1_INT10;
CONNECT735 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT11, CPU1_INT11;
CONNECT736 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT12, CPU1_INT12;
CONNECT737 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT13, CPU1_INT13;
CONNECT738 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT14, CPU1_INT14;
CONNECT739 C66XX_S.CPU_SYSTEM_1.CPU1.PINC, C66XX_S.CPU_SYSTEM_1.CPU1.INT15, CPU1_INT15;
CONNECT740 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT4, CPU2_INT4;
CONNECT741 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT5, CPU2_INT5;
CONNECT742 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT6, CPU2_INT6;
CONNECT743 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT7, CPU2_INT7;
CONNECT744 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT8, CPU2_INT8;
CONNECT745 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT9, CPU2_INT9;
CONNECT746 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT10, CPU2_INT10;
CONNECT747 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT11, CPU2_INT11;
CONNECT748 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT12, CPU2_INT12;
CONNECT749 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT13, CPU2_INT13;
CONNECT750 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT14, CPU2_INT14;
CONNECT751 C66XX_S.CPU_SYSTEM_2.CPU2.PINC, C66XX_S.CPU_SYSTEM_2.CPU2.INT15, CPU2_INT15;
CONNECT752 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT4, CPU3_INT4;
CONNECT753 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT5, CPU3_INT5;
CONNECT754 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT6, CPU3_INT6;
CONNECT755 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT7, CPU3_INT7;
CONNECT756 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT8, CPU3_INT8;
CONNECT757 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT9, CPU3_INT9;
CONNECT758 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT10, CPU3_INT10;
CONNECT759 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT11, CPU3_INT11;
CONNECT760 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT12, CPU3_INT12;
CONNECT761 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT13, CPU3_INT13;
CONNECT762 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT14, CPU3_INT14;
CONNECT763 C66XX_S.CPU_SYSTEM_3.CPU3.PINC, C66XX_S.CPU_SYSTEM_3.CPU3.INT15, CPU3_INT15;
CONNECT764 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT4, CPU4_INT4;
CONNECT765 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT5, CPU4_INT5;
CONNECT766 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT6, CPU4_INT6;
CONNECT767 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT7, CPU4_INT7;
CONNECT768 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT8, CPU4_INT8;
CONNECT769 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT9, CPU4_INT9;
CONNECT770 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT10, CPU4_INT10;
CONNECT771 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT11, CPU4_INT11;
CONNECT772 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT12, CPU4_INT12;
CONNECT773 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT13, CPU4_INT13;
CONNECT774 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT14, CPU4_INT14;
CONNECT775 C66XX_S.CPU_SYSTEM_4.CPU4.PINC, C66XX_S.CPU_SYSTEM_4.CPU4.INT15, CPU4_INT15;
CONNECT776 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT4, CPU5_INT4;
CONNECT777 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT5, CPU5_INT5;
CONNECT778 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT6, CPU5_INT6;
CONNECT779 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT7, CPU5_INT7;
CONNECT780 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT8, CPU5_INT8;
CONNECT781 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT9, CPU5_INT9;
CONNECT782 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT10, CPU5_INT10;
CONNECT783 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT11, CPU5_INT11;
CONNECT784 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT12, CPU5_INT12;
CONNECT785 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT13, CPU5_INT13;
CONNECT786 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT14, CPU5_INT14;
CONNECT787 C66XX_S.CPU_SYSTEM_5.CPU5.PINC, C66XX_S.CPU_SYSTEM_5.CPU5.INT15, CPU5_INT15;
CONNECT788 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT4, CPU6_INT4;
CONNECT789 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT5, CPU6_INT5;
CONNECT790 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT6, CPU6_INT6;
CONNECT791 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT7, CPU6_INT7;
CONNECT792 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT8, CPU6_INT8;
CONNECT793 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT9, CPU6_INT9;
CONNECT794 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT10, CPU6_INT10;
CONNECT795 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT11, CPU6_INT11;
CONNECT796 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT12, CPU6_INT12;
CONNECT797 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT13, CPU6_INT13;
CONNECT798 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT14, CPU6_INT14;
CONNECT799 C66XX_S.CPU_SYSTEM_6.CPU6.PINC, C66XX_S.CPU_SYSTEM_6.CPU6.INT15, CPU6_INT15;
CONNECT800 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT4, CPU7_INT4;
CONNECT801 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT5, CPU7_INT5;
CONNECT802 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT6, CPU7_INT6;
CONNECT803 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT7, CPU7_INT7;
CONNECT804 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT8, CPU7_INT8;
CONNECT805 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT9, CPU7_INT9;
CONNECT806 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT10, CPU7_INT10;
CONNECT807 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT11, CPU7_INT11;
CONNECT808 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT12, CPU7_INT12;
CONNECT809 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT13, CPU7_INT13;
CONNECT810 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT14, CPU7_INT14;
CONNECT811 C66XX_S.CPU_SYSTEM_7.CPU7.PINC, C66XX_S.CPU_SYSTEM_7.CPU7.INT15, CPU7_INT15;
// INTERRUPT Connections
//! Connections of INTSEL with CPU
CONNECT812 System.C66XX_S.CPU_SYSTEM_0.CPU0.EXCEP, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_excep_out;
CONNECT813 System.C66XX_S.CPU_SYSTEM_0.CPU0.NMI, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_nmi_out;
CONNECT814 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT4, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int4_out;
CONNECT815 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT5, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int5_out;
CONNECT816 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT6, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int6_out;
CONNECT817 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT7, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int7_out;
CONNECT818 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT8, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int8_out;
CONNECT819 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT9, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int9_out;
CONNECT820 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT10, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int10_out;
CONNECT821 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT11, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int11_out;
CONNECT822 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT12, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int12_out;
CONNECT823 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT13, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int13_out;
CONNECT824 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT14, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int14_out;
CONNECT825 System.C66XX_S.CPU_SYSTEM_0.CPU0.INT15, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_int15_out;
CONNECT826 System.C66XX_S.CPU_SYSTEM_0.CPU0cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSELintsel_idrop_in;
CONNECT827 System.C66XX_S.CPU_SYSTEM_1.CPU1.EXCEP, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_excep_out;
CONNECT828 System.C66XX_S.CPU_SYSTEM_1.CPU1.NMI, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_nmi_out;
CONNECT829 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT4, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int4_out;
CONNECT830 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT5, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int5_out;
CONNECT831 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT6, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int6_out;
CONNECT832 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT7, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int7_out;
CONNECT833 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT8, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int8_out;
CONNECT834 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT9, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int9_out;
CONNECT835 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT10, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int10_out;
CONNECT836 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT11, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int11_out;
CONNECT837 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT12, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int12_out;
CONNECT838 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT13, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int13_out;
CONNECT839 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT14, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int14_out;
CONNECT840 System.C66XX_S.CPU_SYSTEM_1.CPU1.INT15, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_int15_out;
CONNECT841 System.C66XX_S.CPU_SYSTEM_1.CPU1cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSELintsel_idrop_in;
CONNECT842 System.C66XX_S.CPU_SYSTEM_2.CPU2.EXCEP, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_excep_out;
CONNECT843 System.C66XX_S.CPU_SYSTEM_2.CPU2.NMI, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_nmi_out;
CONNECT844 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT4, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int4_out;
CONNECT845 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT5, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int5_out;
CONNECT846 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT6, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int6_out;
CONNECT847 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT7, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int7_out;
CONNECT848 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT8, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int8_out;
CONNECT849 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT9, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int9_out;
CONNECT850 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT10, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int10_out;
CONNECT851 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT11, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int11_out;
CONNECT852 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT12, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int12_out;
CONNECT853 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT13, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int13_out;
CONNECT854 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT14, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int14_out;
CONNECT855 System.C66XX_S.CPU_SYSTEM_2.CPU2.INT15, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_int15_out;
CONNECT856 System.C66XX_S.CPU_SYSTEM_2.CPU2cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSELintsel_idrop_in;
CONNECT857 System.C66XX_S.CPU_SYSTEM_3.CPU3.EXCEP, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_excep_out;
CONNECT858 System.C66XX_S.CPU_SYSTEM_3.CPU3.NMI, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_nmi_out;
CONNECT859 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT4, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int4_out;
CONNECT860 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT5, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int5_out;
CONNECT861 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT6, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int6_out;
CONNECT862 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT7, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int7_out;
CONNECT863 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT8, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int8_out;
CONNECT864 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT9, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int9_out;
CONNECT865 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT10, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int10_out;
CONNECT866 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT11, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int11_out;
CONNECT867 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT12, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int12_out;
CONNECT868 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT13, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int13_out;
CONNECT869 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT14, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int14_out;
CONNECT870 System.C66XX_S.CPU_SYSTEM_3.CPU3.INT15, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_int15_out;
CONNECT871 System.C66XX_S.CPU_SYSTEM_3.CPU3cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSELintsel_idrop_in;
CONNECT872 System.C66XX_S.CPU_SYSTEM_4.CPU4.EXCEP, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_excep_out;
CONNECT873 System.C66XX_S.CPU_SYSTEM_4.CPU4.NMI, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_nmi_out;
CONNECT874 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT4, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int4_out;
CONNECT875 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT5, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int5_out;
CONNECT876 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT6, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int6_out;
CONNECT877 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT7, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int7_out;
CONNECT878 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT8, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int8_out;
CONNECT879 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT9, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int9_out;
CONNECT880 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT10, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int10_out;
CONNECT881 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT11, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int11_out;
CONNECT882 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT12, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int12_out;
CONNECT883 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT13, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int13_out;
CONNECT884 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT14, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int14_out;
CONNECT885 System.C66XX_S.CPU_SYSTEM_4.CPU4.INT15, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_int15_out;
CONNECT886 System.C66XX_S.CPU_SYSTEM_4.CPU4cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSELintsel_idrop_in;
CONNECT887 System.C66XX_S.CPU_SYSTEM_5.CPU5.EXCEP, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_excep_out;
CONNECT888 System.C66XX_S.CPU_SYSTEM_5.CPU5.NMI, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_nmi_out;
CONNECT889 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT4, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int4_out;
CONNECT890 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT5, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int5_out;
CONNECT891 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT6, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int6_out;
CONNECT892 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT7, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int7_out;
CONNECT893 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT8, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int8_out;
CONNECT894 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT9, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int9_out;
CONNECT895 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT10, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int10_out;
CONNECT896 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT11, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int11_out;
CONNECT897 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT12, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int12_out;
CONNECT898 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT13, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int13_out;
CONNECT899 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT14, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int14_out;
CONNECT900 System.C66XX_S.CPU_SYSTEM_5.CPU5.INT15, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_int15_out;
CONNECT901 System.C66XX_S.CPU_SYSTEM_5.CPU5cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSELintsel_idrop_in;
CONNECT902 System.C66XX_S.CPU_SYSTEM_6.CPU6.EXCEP, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_excep_out;
CONNECT903 System.C66XX_S.CPU_SYSTEM_6.CPU6.NMI, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_nmi_out;
CONNECT904 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT4, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int4_out;
CONNECT905 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT5, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int5_out;
CONNECT906 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT6, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int6_out;
CONNECT907 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT7, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int7_out;
CONNECT908 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT8, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int8_out;
CONNECT909 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT9, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int9_out;
CONNECT910 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT10, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int10_out;
CONNECT911 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT11, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int11_out;
CONNECT912 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT12, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int12_out;
CONNECT913 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT13, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int13_out;
CONNECT914 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT14, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int14_out;
CONNECT915 System.C66XX_S.CPU_SYSTEM_6.CPU6.INT15, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_int15_out;
CONNECT916 System.C66XX_S.CPU_SYSTEM_6.CPU6cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSELintsel_idrop_in;
CONNECT917 System.C66XX_S.CPU_SYSTEM_7.CPU7.EXCEP, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_excep_out;
CONNECT918 System.C66XX_S.CPU_SYSTEM_7.CPU7.NMI, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_nmi_out;
CONNECT919 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT4, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int4_out;
CONNECT920 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT5, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int5_out;
CONNECT921 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT6, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int6_out;
CONNECT922 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT7, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int7_out;
CONNECT923 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT8, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int8_out;
CONNECT924 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT9, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int9_out;
CONNECT925 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT10, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int10_out;
CONNECT926 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT11, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int11_out;
CONNECT927 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT12, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int12_out;
CONNECT928 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT13, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int13_out;
CONNECT929 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT14, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int14_out;
CONNECT930 System.C66XX_S.CPU_SYSTEM_7.CPU7.INT15, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_int15_out;
CONNECT931 System.C66XX_S.CPU_SYSTEM_7.CPU7cpu_idropped_out, System.C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSELintsel_idrop_in;
// System Interrupt Connections - INTC0
//EDMA1
CONNECT932 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in0, C66XX_S.SHARED_SYSTEM.EDMA_1.errint_out_pin;
CONNECT933 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in6, C66XX_S.SHARED_SYSTEM.EDMA_1_gint_out_pin;
CONNECT934 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in8, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin0;
CONNECT935 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in9, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin1;
CONNECT936 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in10, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin2;
CONNECT937 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in11, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin3;
CONNECT938 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in12, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin4;
CONNECT939 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in13, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin5;
CONNECT940 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in14, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin6;
CONNECT941 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in15, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin7;
//EDMA2
CONNECT942 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in16, C66XX_S.SHARED_SYSTEM.EDMA_2.errint_out_pin;
CONNECT943 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in22, C66XX_S.SHARED_SYSTEM.EDMA_2_gint_out_pin;
CONNECT944 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in24, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin0;
CONNECT945 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in25, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin1;
CONNECT946 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in26, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin2;
CONNECT947 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in27, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin3;
CONNECT948 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in28, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin4;
CONNECT949 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in29, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin5;
CONNECT950 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in30, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin6;
CONNECT951 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in31, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin7;
//EDMA0
CONNECT952 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in32, C66XX_S.SHARED_SYSTEM.EDMA_0.errint_out_pin;
CONNECT953 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in36, C66XX_S.SHARED_SYSTEM.EDMA_0_gint_out_pin;
CONNECT954 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in38, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin0;
CONNECT955 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in39, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin1;
CONNECT956 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in40, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin2;
CONNECT957 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in41, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin3;
CONNECT958 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in42, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin4;
CONNECT959 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in43, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin5;
CONNECT960 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in44, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin6;
CONNECT961 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in45, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin7;
//SRIO
CONNECT962 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in112, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr0;
CONNECT963 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in113, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr1;
CONNECT964 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in114, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr2;
CONNECT965 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in115, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr3;
CONNECT966 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in116, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr4;
CONNECT967 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in117, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr5;
CONNECT968 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in118, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr6;
CONNECT969 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in119, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr7;
CONNECT970 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in120, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr8;
CONNECT971 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in121, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr9;
CONNECT972 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in122, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr10;
CONNECT973 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in123, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr11;
CONNECT974 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in124, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr12;
CONNECT975 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in125, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr13;
CONNECT976 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in126, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr14;
CONNECT977 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in127, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr15;
//QUEUE_MANAGER
//CONNECT574 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in133, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.;
//CONNECT575 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in134, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.;
//CONNECT575 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in135, C66XX_S.SHARED_SYSTEM.SRIO.;
// System Interrupt Connections - INTC1
//EDMA1
CONNECT978 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in0, C66XX_S.SHARED_SYSTEM.EDMA_1.errint_out_pin;
CONNECT979 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in6, C66XX_S.SHARED_SYSTEM.EDMA_1_gint_out_pin;
CONNECT980 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in8, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin0;
CONNECT981 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in9, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin1;
CONNECT982 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in10, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin2;
CONNECT983 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in11, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin3;
CONNECT984 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in12, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin4;
CONNECT985 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in13, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin5;
CONNECT986 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in14, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin6;
CONNECT987 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in15, C66XX_S.SHARED_SYSTEM.EDMA_1_int_out_pin7;
//EDMA2
CONNECT988 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in16, C66XX_S.SHARED_SYSTEM.EDMA_2.errint_out_pin;
CONNECT989 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in22, C66XX_S.SHARED_SYSTEM.EDMA_2_gint_out_pin;
CONNECT990 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in24, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin0;
CONNECT991 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in25, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin1;
CONNECT992 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in26, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin2;
CONNECT993 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in27, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin3;
CONNECT994 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in28, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin4;
CONNECT995 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in29, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin5;
CONNECT996 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in30, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin6;
CONNECT997 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in31, C66XX_S.SHARED_SYSTEM.EDMA_2_int_out_pin7;
//EDMA0
CONNECT998 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in32, C66XX_S.SHARED_SYSTEM.EDMA_0.errint_out_pin;
CONNECT999 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in36, C66XX_S.SHARED_SYSTEM.EDMA_0_gint_out_pin;
CONNECT1000 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in38, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin0;
CONNECT1001 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in39, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin1;
CONNECT1002 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in40, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin2;
CONNECT1003 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in41, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin3;
CONNECT1004 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in42, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin4;
CONNECT1005 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in43, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin5;
CONNECT1006 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in44, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin6;
CONNECT1007 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in45, C66XX_S.SHARED_SYSTEM.EDMA_0_int_out_pin7;
//SRIO
CONNECT1008 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in112, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr0;
CONNECT1009 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in113, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr1;
CONNECT1010 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in114, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr2;
CONNECT1011 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in115, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr3;
CONNECT1012 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in116, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr4;
CONNECT1013 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in117, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr5;
CONNECT1014 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in118, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr6;
CONNECT1015 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in119, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr7;
CONNECT1016 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in120, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr8;
CONNECT1017 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in121, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr9;
CONNECT1018 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in122, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr10;
CONNECT1019 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in123, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr11;
CONNECT1020 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in124, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr12;
CONNECT1021 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in125, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr13;
CONNECT1022 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in126, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr14;
CONNECT1023 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in127, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr15;
//QUEUE_MANAGER
//CONNECT574 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in133, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.;
//CONNECT575 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in134, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.;
//CONNECT575 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in135, C66XX_S.SHARED_SYSTEM.SRIO.;
// System Interrupt Connections - INTC2
//GPIO
CONNECT1024 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in0, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1025 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in1, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1026 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in2, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1027 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in3, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1028 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in4, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1029 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in5, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1030 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in6, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1031 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in7, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
//QUEUE_MANAGER
CONNECT1032 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in24, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_16_opin;
CONNECT1033 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in25, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_17_opin;
CONNECT1034 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in26, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_18_opin;
CONNECT1035 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in27, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_19_opin;
CONNECT1036 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in28, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_20_opin;
CONNECT1037 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in29, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_21_opin;
CONNECT1038 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in30, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_22_opin;
CONNECT1039 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in31, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_23_opin;
CONNECT1040 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_24_opin;
CONNECT1041 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_25_opin;
CONNECT1042 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_26_opin;
CONNECT1043 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_27_opin;
CONNECT1044 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_28_opin;
CONNECT1045 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_29_opin;
CONNECT1046 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_30_opin;
CONNECT1047 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in58, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin0;
CONNECT1048 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_31_opin;
CONNECT1049 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in134, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin4;
CONNECT1050 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in135, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin5;
CONNECT1051 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in136, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin6;
CONNECT1052 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in137, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin7;
CONNECT1053 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in138, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_0_opin;
CONNECT1054 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in139, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_1_opin;
CONNECT1055 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in140, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_2_opin;
CONNECT1056 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in141, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_3_opin;
CONNECT1057 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in142, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_4_opin;
CONNECT1058 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in143, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_5_opin;
CONNECT1059 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in144, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_6_opin;
CONNECT1060 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in145, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_7_opin;
CONNECT1061 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in146, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_8_opin;
CONNECT1062 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in147, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_9_opin;
CONNECT1063 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in148, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_10_opin;
CONNECT1064 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in149, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_11_opin;
CONNECT1065 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in150, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_12_opin;
CONNECT1066 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in151, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_13_opin;
CONNECT1067 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in152, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_14_opin;
CONNECT1068 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in153, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_15_opin;
//SEMAPHORE
CONNECT1069 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in58, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin0;
CONNECT1070 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in59, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin1;
CONNECT1071 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in60, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin2;
CONNECT1072 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in61, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin3;
//SRIO
CONNECT1073 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in93, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr0;
CONNECT1074 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in94, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr1;
CONNECT1075 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in95, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr2;
CONNECT1076 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in96, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr3;
CONNECT1077 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in97, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr4;
CONNECT1078 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in98, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr5;
CONNECT1079 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in99, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr6;
CONNECT1080 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in100, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr7;
CONNECT1081 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in101, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr8;
CONNECT1082 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in102, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr9;
CONNECT1083 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in103, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr10;
CONNECT1084 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in104, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr11;
CONNECT1085 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in105, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr12;
CONNECT1086 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in106, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr13;
CONNECT1087 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in107, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr14;
CONNECT1088 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in108, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr15;
CONNECT1089 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in109, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr16;
CONNECT1090 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in110, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr17;
CONNECT1091 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in111, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr18;
CONNECT1092 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in112, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr19;
CONNECT1093 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in113, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr20;
CONNECT1094 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in114, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr21;
CONNECT1095 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in115, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr22;
CONNECT1096 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in116, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr23;
// System Interrupt Connections - INTC3
//GPIO
CONNECT1097 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in0, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
CONNECT1098 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in1, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
CONNECT1099 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in2, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT1100 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in3, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
CONNECT1101 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in4, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT1102 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in5, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT1103 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in6, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT1104 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in7, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
CONNECT1105 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in8, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1106 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in9, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1107 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in10, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1108 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in11, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1109 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in12, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1110 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in13, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1111 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in14, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1112 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_system_intr_in15, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
// Host Interrupt Connections for INTC0
//! With CGEM_0
// CONNECT1078 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out0, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_60;
// CONNECT1079 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out1, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_61;
CONNECT1113 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out2, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_62;
CONNECT1114 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out3, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_63;
CONNECT1115 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out4, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_92;
CONNECT1116 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out5, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_93;
CONNECT1117 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out6, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_94;
CONNECT1118 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out7, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_95;
CONNECT1119 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out32, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_21;
CONNECT1120 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out33, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_22;
CONNECT1121 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out34, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_23;
CONNECT1122 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out35, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_24;
CONNECT1123 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out36, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_25;
CONNECT1124 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out37, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_26;
CONNECT1125 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out38, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_27;
CONNECT1126 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out39, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_28;
CONNECT1127 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out40, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_29;
CONNECT1128 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out41, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_30;
CONNECT1129 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out42, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_31;
//! With CGEM_1
// CONNECT1097 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out8, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_60;
// CONNECT1098 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out9, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_61;
CONNECT1130 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out10, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_62;
CONNECT1131 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out11, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_63;
CONNECT1132 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out12, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_92;
CONNECT1133 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out13, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_93;
CONNECT1134 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out14, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_94;
CONNECT1135 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out15, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_95;
CONNECT1136 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out43, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_21;
CONNECT1137 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out44, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_22;
CONNECT1138 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out45, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_23;
CONNECT1139 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out46, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_24;
CONNECT1140 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out47, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_25;
CONNECT1141 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out48, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_26;
CONNECT1142 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out49, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_27;
CONNECT1143 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out50, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_28;
CONNECT1144 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out51, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_29;
CONNECT1145 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out52, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_30;
CONNECT1146 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out53, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_31;
//! With CGEM_2
// CONNECT1116 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out16, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_60;
// CONNECT1117 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out17, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_61;
CONNECT1147 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out18, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_62;
CONNECT1148 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out19, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_63;
CONNECT1149 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out20, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_92;
CONNECT1150 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out21, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_93;
CONNECT1151 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out22, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_94;
CONNECT1152 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out23, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_95;
CONNECT1153 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out54, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_21;
CONNECT1154 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out55, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_22;
CONNECT1155 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out56, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_23;
CONNECT1156 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out57, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_24;
CONNECT1157 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out58, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_25;
CONNECT1158 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out59, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_26;
CONNECT1159 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out60, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_27;
CONNECT1160 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out61, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_28;
CONNECT1161 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out62, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_29;
CONNECT1162 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out63, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_30;
CONNECT1163 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out64, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_31;
//! With CGEM_3
// CONNECT1135 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out24, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_60;
// CONNECT1136 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out25, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_61;
CONNECT1164 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out26, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_62;
CONNECT1165 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out27, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_63;
CONNECT1166 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out28, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_92;
CONNECT1167 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out29, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_93;
CONNECT1168 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out30, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_94;
CONNECT1169 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out31, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_95;
CONNECT1170 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out65, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_21;
CONNECT1171 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out66, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_22;
CONNECT1172 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out67, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_23;
CONNECT1173 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out68, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_24;
CONNECT1174 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out69, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_25;
CONNECT1175 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out70, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_26;
CONNECT1176 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out71, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_27;
CONNECT1177 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out72, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_28;
CONNECT1178 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out73, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_29;
CONNECT1179 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out74, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_30;
CONNECT1180 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out75, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_31;
// Host Interrupt Connections for INTC1
//! With CGEM_4
// CONNECT1154 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out0, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_60;
// CONNECT1155 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out1, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_61;
CONNECT1181 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out2, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_62;
CONNECT1182 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out3, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_63;
CONNECT1183 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out4, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_92;
CONNECT1184 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out5, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_93;
CONNECT1185 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out6, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_94;
CONNECT1186 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out7, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_95;
CONNECT1187 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out32, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_21;
CONNECT1188 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out33, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_22;
CONNECT1189 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out34, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_23;
CONNECT1190 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out35, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_24;
CONNECT1191 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out36, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_25;
CONNECT1192 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out37, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_26;
CONNECT1193 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out38, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_27;
CONNECT1194 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out39, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_28;
CONNECT1195 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out40, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_29;
CONNECT1196 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out41, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_30;
CONNECT1197 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out42, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_31;
//! With CGEM_5
// CONNECT1173 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out8, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_60;
// CONNECT1174 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out9, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_61;
CONNECT1198 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out10, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_62;
CONNECT1199 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out11, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_63;
CONNECT1200 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out12, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_92;
CONNECT1201 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out13, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_93;
CONNECT1202 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out14, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_94;
CONNECT1203 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out15, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_95;
CONNECT1204 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out43, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_21;
CONNECT1205 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out44, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_22;
CONNECT1206 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out45, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_23;
CONNECT1207 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out46, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_24;
CONNECT1208 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out47, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_25;
CONNECT1209 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out48, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_26;
CONNECT1210 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out49, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_27;
CONNECT1211 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out50, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_28;
CONNECT1212 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out51, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_29;
CONNECT1213 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out52, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_30;
CONNECT1214 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out53, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_31;
//! With CGEM_6
// CONNECT1192 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out16, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_60;
// CONNECT1193 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out17, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_61;
CONNECT1215 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out18, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_62;
CONNECT1216 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out19, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_63;
CONNECT1217 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out20, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_92;
CONNECT1218 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out21, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_93;
CONNECT1219 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out22, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_94;
CONNECT1220 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out23, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_95;
CONNECT1221 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out54, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_21;
CONNECT1222 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out55, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_22;
CONNECT1223 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out56, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_23;
CONNECT1224 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out57, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_24;
CONNECT1225 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out58, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_25;
CONNECT1226 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out59, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_26;
CONNECT1227 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out60, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_27;
CONNECT1228 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out61, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_28;
CONNECT1229 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out62, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_29;
CONNECT1230 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out63, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_30;
CONNECT1231 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out64, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_31;
//! With CGEM_7
// CONNECT1211 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out24, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_60;
// CONNECT1212 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out25, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_61;
CONNECT1232 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out26, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_62;
CONNECT1233 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out27, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_63;
CONNECT1234 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out28, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_92;
CONNECT1235 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out29, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_93;
CONNECT1236 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out30, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_94;
CONNECT1237 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out31, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_95;
CONNECT1238 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out65, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_21;
CONNECT1239 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out66, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_22;
CONNECT1240 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out67, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_23;
CONNECT1241 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out68, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_24;
CONNECT1242 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out69, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_25;
CONNECT1243 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out70, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_26;
CONNECT1244 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out71, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_27;
CONNECT1245 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out72, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_28;
CONNECT1246 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out73, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_29;
CONNECT1247 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out74, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_30;
CONNECT1248 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out75, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_31;
// Host Interrupt Connections for INTC2
//! With EDMA_1
CONNECT1249 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out0, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin42;
CONNECT1250 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out1, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin43;
CONNECT1251 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out2, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin44;
CONNECT1252 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out3, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin45;
CONNECT1253 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out4, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin46;
CONNECT1254 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out5, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin47;
CONNECT1255 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out6, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin48;
CONNECT1256 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out7, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin49;
CONNECT1257 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out8, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin50;
CONNECT1258 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out9, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin51;
CONNECT1259 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out10, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin52;
CONNECT1260 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out11, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin53;
CONNECT1261 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out12, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin54;
CONNECT1262 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out13, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin55;
CONNECT1263 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out14, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin56;
CONNECT1264 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out15, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin57;
CONNECT1265 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out16, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin58;
CONNECT1266 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out17, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin59;
CONNECT1267 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out18, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin60;
CONNECT1268 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out19, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin61;
CONNECT1269 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out20, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin62;
CONNECT1270 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out21, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin63;
CONNECT1271 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out44, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin38;
CONNECT1272 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out45, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin39;
CONNECT1273 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out46, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin40;
CONNECT1274 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out47, C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin41;
//! With EDMA_2
CONNECT1275 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out22, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin42;
CONNECT1276 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out23, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin43;
CONNECT1277 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out24, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin44;
CONNECT1278 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out25, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin45;
CONNECT1279 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out26, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin46;
CONNECT1280 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out27, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin47;
CONNECT1281 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out28, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin48;
CONNECT1282 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out29, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin49;
CONNECT1283 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out30, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin50;
CONNECT1284 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out31, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin51;
CONNECT1285 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out32, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin52;
CONNECT1286 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out33, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin53;
CONNECT1287 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out34, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin54;
CONNECT1288 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out35, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin55;
CONNECT1289 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out36, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin56;
CONNECT1290 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out37, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin57;
CONNECT1291 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out38, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin58;
CONNECT1292 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out39, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin59;
CONNECT1293 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out40, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin60;
CONNECT1294 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out41, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin61;
CONNECT1295 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out42, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin62;
CONNECT1296 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out43, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin63;
CONNECT1297 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out48, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin38;
CONNECT1298 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out49, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin39;
CONNECT1299 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out50, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin40;
CONNECT1300 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_out51, C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin41;
// Host Interrupt Connections for INTC3
//! With EDMA_0
CONNECT1301 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out0, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin8;
CONNECT1302 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out1, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin9;
CONNECT1303 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out2, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin10;
CONNECT1304 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out3, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin11;
CONNECT1305 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out4, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin12;
CONNECT1306 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out5, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin13;
CONNECT1307 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out6, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin14;
CONNECT1308 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_out7, C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin15;
// Primary Interrupt Connections with CPU
//!CPU0
//SEMAPHORE
CONNECT1309 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin0;
CONNECT1310 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin0;
//SRIO
CONNECT1311 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr16;
//QUEUE_MANAGER
CONNECT1312 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1313 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1314 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1315 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1316 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1317 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1318 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1319 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1320 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1321 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1322 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1323 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1324 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1325 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1326 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1327 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1328 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_0_opin;
CONNECT1329 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_8_opin;
CONNECT1330 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_16_opin;
CONNECT1331 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_24_opin;
//TIMERS
CONNECT1332 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_0_cpu_int_12;
CONNECT1333 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_0_cpu_int_34;
CONNECT1334 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1335 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1336 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1337 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1338 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1339 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1340 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1341 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1342 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1343 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1344 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1345 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1346 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1347 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1348 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1349 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1350 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1351 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1352 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1353 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1354 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1355 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1356 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1357 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1358 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
//IPC
CONNECT1359 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_0;
//!CPU1
//SEMAPHORE
CONNECT1360 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin1;
CONNECT1361 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin1;
//SRIO
CONNECT1362 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr17;
//QUEUE_MANAGER
CONNECT1363 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1364 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1365 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1366 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1367 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1368 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1369 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1370 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1371 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1372 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1373 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1374 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1375 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1376 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1377 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1378 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1379 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_1_opin;
CONNECT1380 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_9_opin;
CONNECT1381 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_17_opin;
CONNECT1382 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_25_opin;
//TIMERS
CONNECT1383 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_1_cpu_int_12;
CONNECT1384 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_1_cpu_int_34;
CONNECT1385 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1386 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1387 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1388 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1389 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1390 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1391 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1392 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1393 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1394 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1395 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1396 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1397 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1398 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1399 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1400 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1401 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1402 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1403 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1404 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1405 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1406 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1407 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1408 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1409 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
//IPC
CONNECT1410 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_1;
//!CPU2
//SEMAPHORE
CONNECT1411 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin2;
CONNECT1412 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin2;
//SRIO
CONNECT1413 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr18;
//QUEUE_MANAGER
CONNECT1414 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1415 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1416 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1417 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1418 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1419 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1420 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1421 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1422 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1423 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1424 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1425 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1426 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1427 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1428 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1429 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1430 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_2_opin;
CONNECT1431 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_10_opin;
CONNECT1432 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_18_opin;
CONNECT1433 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_26_opin;
//TIMERS
CONNECT1434 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_2_cpu_int_12;
CONNECT1435 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_2_cpu_int_34;
CONNECT1436 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1437 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1438 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1439 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1440 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1441 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1442 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1443 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1444 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1445 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1446 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1447 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1448 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1449 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1450 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1451 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1452 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1453 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1454 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1455 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1456 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1457 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1458 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1459 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1460 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
//IPC
CONNECT1461 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_2;
//!CPU3
//SEMAPHORE
CONNECT1462 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin3;
CONNECT1463 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin3;
//SRIO
CONNECT1464 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr19;
//QUEUE_MANAGER
CONNECT1465 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1466 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1467 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1468 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1469 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1470 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1471 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1472 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1473 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1474 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1475 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1476 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1477 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1478 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1479 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1480 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1481 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_3_opin;
CONNECT1482 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_11_opin;
CONNECT1483 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_19_opin;
CONNECT1484 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_27_opin;
//TIMERS
CONNECT1485 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_3_cpu_int_12;
CONNECT1486 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_3_cpu_int_34;
CONNECT1487 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1488 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1489 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1490 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1491 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1492 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1493 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1494 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1495 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1496 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1497 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1498 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1499 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1500 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1501 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1502 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1503 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1504 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1505 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1506 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1507 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1508 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1509 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1510 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1511 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
//IPC
CONNECT1512 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_3;
//!CPU4
//SEMAPHORE
CONNECT1513 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin4;
CONNECT1514 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin4;
//SRIO
CONNECT1515 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr20;
//QUEUE_MANAGER
CONNECT1516 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1517 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1518 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1519 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1520 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1521 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1522 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1523 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1524 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1525 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1526 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1527 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1528 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1529 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1530 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1531 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1532 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_4_opin;
CONNECT1533 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_12_opin;
CONNECT1534 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_20_opin;
CONNECT1535 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_28_opin;
//TIMERS
CONNECT1536 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_4_cpu_int_12;
CONNECT1537 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_4_cpu_int_34;
CONNECT1538 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1539 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1540 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1541 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1542 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1543 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1544 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1545 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1546 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1547 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1548 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1549 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1550 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1551 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1552 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1553 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1554 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1555 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1556 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1557 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1558 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1559 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1560 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1561 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1562 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
//IPC
CONNECT1563 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_4;
//!CPU5
//SEMAPHORE
CONNECT1564 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin5;
CONNECT1565 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin5;
//SRIO
CONNECT1566 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr21;
//QUEUE_MANAGER
CONNECT1567 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1568 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1569 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1570 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1571 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1572 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1573 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1574 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1575 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1576 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1577 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1578 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1579 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1580 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1581 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1582 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1583 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_5_opin;
CONNECT1584 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_13_opin;
CONNECT1585 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_21_opin;
CONNECT1586 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_29_opin;
//TIMERS
CONNECT1587 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_5_cpu_int_12;
CONNECT1588 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_5_cpu_int_34;
CONNECT1589 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1590 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1591 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1592 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1593 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1594 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1595 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1596 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1597 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1598 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1599 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1600 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1601 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1602 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1603 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1604 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1605 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1606 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1607 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1608 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1609 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1610 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1611 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1612 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1613 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
//IPC
CONNECT1614 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_5;
//!CPU6
//SEMAPHORE
CONNECT1615 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin6;
CONNECT1616 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin6;
//SRIO
CONNECT1617 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr22;
//QUEUE_MANAGER
CONNECT1618 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1619 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1620 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1621 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1622 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1623 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1624 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1625 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1626 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1627 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1628 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1629 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1630 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1631 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1632 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1633 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1634 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_6_opin;
CONNECT1635 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_14_opin;
CONNECT1636 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_22_opin;
CONNECT1637 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_30_opin;
//TIMERS
CONNECT1638 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_6_cpu_int_12;
CONNECT1639 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_6_cpu_int_34;
CONNECT1640 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1641 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1642 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1643 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1644 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1645 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1646 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1647 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1648 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1649 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1650 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1651 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1652 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1653 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1654 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1655 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1656 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1657 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1658 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1659 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1660 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1661 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1662 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1663 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1664 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
//IPC
CONNECT1665 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_6;
//!CPU7
//SEMAPHORE
CONNECT1666 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_err_opin7;
CONNECT1667 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin7;
//SRIO
CONNECT1668 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_20, C66XX_S.SHARED_SYSTEM.SRIO.srio_intdst_intr23;
//QUEUE_MANAGER
CONNECT1669 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_32, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_0_opin;
CONNECT1670 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_33, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_1_opin;
CONNECT1671 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_34, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_2_opin;
CONNECT1672 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_35, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_3_opin;
CONNECT1673 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_36, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_4_opin;
CONNECT1674 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_37, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_5_opin;
CONNECT1675 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_38, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_6_opin;
CONNECT1676 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_39, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_7_opin;
CONNECT1677 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_40, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_8_opin;
CONNECT1678 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_41, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_9_opin;
CONNECT1679 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_42, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_10_opin;
CONNECT1680 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_43, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_11_opin;
CONNECT1681 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_44, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_12_opin;
CONNECT1682 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_45, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_13_opin;
CONNECT1683 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_46, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_14_opin;
CONNECT1684 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_47, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int0_15_opin;
CONNECT1685 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_48, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_7_opin;
CONNECT1686 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_49, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_15_opin;
CONNECT1687 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_50, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_23_opin;
CONNECT1688 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_51, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int1_31_opin;
//TIMERS
CONNECT1689 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_64, C66XX_S.SHARED_SYSTEM.TIMER64_7_cpu_int_12;
CONNECT1690 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_65, C66XX_S.SHARED_SYSTEM.TIMER64_7_cpu_int_34;
CONNECT1691 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_66, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1692 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_67, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1693 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_68, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1694 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_69, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1695 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_70, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1696 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_71, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1697 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_72, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1698 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_73, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1699 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_74, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1700 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_75, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1701 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_76, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1702 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_77, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1703 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_78, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1704 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_79, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1705 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_80, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1706 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_81, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
//GPIO
CONNECT1707 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_82, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint8_opin;
CONNECT1708 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_83, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint9_opin;
CONNECT1709 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_84, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint10_opin;
CONNECT1710 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_85, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint11_opin;
CONNECT1711 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_86, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint12_opin;
CONNECT1712 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_87, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint13_opin;
CONNECT1713 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_88, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint14_opin;
CONNECT1714 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_89, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint15_opin;
CONNECT1715 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_90, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
//IPC
CONNECT1716 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_91, C66XX_S.SHARED_SYSTEM.IPC_cpu_int_7;
// Primary Interrupt Connections with EDMA_1
//GPIO
CONNECT1717 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin6, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
CONNECT1718 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin7, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
CONNECT1719 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin8, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT1720 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin9, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
CONNECT1721 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin10, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT1722 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin11, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT1723 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin12, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT1724 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin13, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
//SEMAPHORE
CONNECT1725 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin14, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin0;
CONNECT1726 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin1;
CONNECT1727 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin2;
CONNECT1728 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin17, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin3;
CONNECT1729 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin18, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin4;
CONNECT1730 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin19, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin5;
CONNECT1731 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin20, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin6;
CONNECT1732 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin21, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin7;
//TIMER64
CONNECT1733 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin22, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1734 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin23, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1735 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin24, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1736 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin25, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1737 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin26, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1738 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin27, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1739 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin28, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1740 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin29, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1741 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin30, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1742 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin31, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1743 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin32, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1744 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin33, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1745 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin34, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1746 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin35, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1747 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin36, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1748 C66XX_S.SHARED_SYSTEM.EDMA_1_evt_in_pin37, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
// Primary Interrupt Connections with EDMA_2
//GPIO
CONNECT1749 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin6, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint0_opin;
CONNECT1750 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin7, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint1_opin;
CONNECT1751 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin8, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint2_opin;
CONNECT1752 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin9, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint3_opin;
CONNECT1753 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin10, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint4_opin;
CONNECT1754 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin11, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint5_opin;
CONNECT1755 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin12, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint6_opin;
CONNECT1756 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin13, C66XX_S.SHARED_SYSTEM.GPIO.gpio_gpint7_opin;
//SEMAPHORE
CONNECT1757 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin14, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin0;
CONNECT1758 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin15, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin1;
CONNECT1759 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin16, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin2;
CONNECT1760 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin17, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin3;
CONNECT1761 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin18, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin4;
CONNECT1762 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin19, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin5;
CONNECT1763 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin20, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin6;
CONNECT1764 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin21, C66XX_S.SHARED_SYSTEM.SEMAPHORE.semaphore2_intr_opin7;
//TIMER64
CONNECT1765 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin22, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1766 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin23, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1767 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin24, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1768 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin25, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1769 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin26, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1770 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin27, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1771 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin28, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1772 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin29, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1773 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin30, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_12;
CONNECT1774 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin31, C66XX_S.SHARED_SYSTEM.TIMER64_12_cpu_int_34;
CONNECT1775 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin32, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_12;
CONNECT1776 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin33, C66XX_S.SHARED_SYSTEM.TIMER64_13_cpu_int_34;
CONNECT1777 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin34, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_12;
CONNECT1778 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin35, C66XX_S.SHARED_SYSTEM.TIMER64_14_cpu_int_34;
CONNECT1779 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin36, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_12;
CONNECT1780 C66XX_S.SHARED_SYSTEM.EDMA_2_evt_in_pin37, C66XX_S.SHARED_SYSTEM.TIMER64_15_cpu_int_34;
// Primary Interrupt Connections with EDMA_0
//TIMER64
CONNECT1781 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin0, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_12;
CONNECT1782 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin1, C66XX_S.SHARED_SYSTEM.TIMER64_8_cpu_int_34;
CONNECT1783 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin2, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_12;
CONNECT1784 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin3, C66XX_S.SHARED_SYSTEM.TIMER64_9_cpu_int_34;
CONNECT1785 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin4, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_12;
CONNECT1786 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin5, C66XX_S.SHARED_SYSTEM.TIMER64_10_cpu_int_34;
CONNECT1787 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin6, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_12;
CONNECT1788 C66XX_S.SHARED_SYSTEM.EDMA_0_evt_in_pin7, C66XX_S.SHARED_SYSTEM.TIMER64_11_cpu_int_34;
CONNECT1789 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.BOOT_ROM_mif, 0x20B00000, 0x20B1FFFF, 0;
CONNECT1790 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.BOOT_ROM_mif, 0x20B00000, 0x20B1FFFF, 0;
CONNECT1791 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.BOOT_ROM_mif, 0x20B00000, 0x20B1FFFF, 0;
CONNECT1792 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.BOOT_ROM_mif, 0x20B00000, 0x20B1FFFF, 0;
// Interrupt connections for PA_SS
//! with INTC0
CONNECT1793 C66XX_S.SHARED_SYSTEM.PASS.pass_intr_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in72;
//! with INTC1
CONNECT1794 C66XX_S.SHARED_SYSTEM.PASS.pass_intr_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in72;
//! with INTC2
CONNECT1795 C66XX_S.SHARED_SYSTEM.PASS.pass_intr_opin, C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_system_intr_in44;
// PASS memory master connections
CONNECT1796 C66XX_S.SHARED_SYSTEM.PASS.pass_read_opin, C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_read_ipin;
CONNECT1797 C66XX_S.SHARED_SYSTEM.PASS.pass_write_opin, C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_write_ipin;
CONNECT1798 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT1799 C66XX_S.SHARED_SYSTEM.MEMTR_PASS_Master.MT_SSI2MMAP.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT1800 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT1801 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT1802 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT1803 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT1804 C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT1805 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT1806 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT1807 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT1808 C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT1809 C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT1810 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT1811 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT1812 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_dbg_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT1813 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_dbg_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC0_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT1814 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT1815 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT1816 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_dbg_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT1817 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_dbg_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC1_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT1818 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT1819 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT1820 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_dbg_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT1821 C66XX_S.SHARED_SYSTEM.CP_INTC2.cp_intc_dbg_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC2_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT1822 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT1823 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT1824 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_dbg_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT1825 C66XX_S.SHARED_SYSTEM.CP_INTC3.cp_intc_dbg_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_CP_INTC3_Config.MT_MIF2SSI.memtr_dbg_write_opin;
CONNECT1826 C66XX_S.SHARED_SYSTEM.IPC.ici_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_read_opin;
CONNECT1827 C66XX_S.SHARED_SYSTEM.IPC.ici_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_write_opin;
CONNECT1828 C66XX_S.SHARED_SYSTEM.IPC.ici_dbg_read_in, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_dbg_read_opin;
CONNECT1829 C66XX_S.SHARED_SYSTEM.IPC.ici_dbg_write_in, C66XX_S.SHARED_SYSTEM.MEMTR_IPC_Config.MT_MIF2SSI.memtr_dbg_write_opin;
//Addition in jan 2010, additional QMSS interrupts
CONNECT1830 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_12_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in47;
CONNECT1831 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_13_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in91;
CONNECT1832 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_14_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in93;
CONNECT1833 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_15_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in95;
CONNECT1834 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_16_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in97;
CONNECT1835 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_17_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in151;
CONNECT1836 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_18_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in152;
CONNECT1837 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_19_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in153;
CONNECT1838 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_20_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in154;
CONNECT1839 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_21_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in155;
CONNECT1840 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_22_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in156;
CONNECT1841 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_23_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in157;
CONNECT1842 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_24_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in158;
CONNECT1843 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_25_opin, C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_system_intr_in159;
CONNECT1844 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_18_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in47;
CONNECT1845 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_19_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in91;
CONNECT1846 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_20_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in93;
CONNECT1847 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_21_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in95;
CONNECT1848 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_22_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in97;
CONNECT1849 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_23_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in151;
CONNECT1850 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_24_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in152;
CONNECT1851 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_25_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in153;
CONNECT1852 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_26_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in154;
CONNECT1853 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_27_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in155;
CONNECT1854 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_28_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in156;
CONNECT1855 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_29_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in157;
CONNECT1856 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_30_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in158;
CONNECT1857 C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_int_pa_tx_31_opin, C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_system_intr_in159;
//PSC
CONNECT1858 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_mif_opin, 0x02350000, 0x02350FFF, -0x02350000;
CONNECT1859 System.SimBridge.global_reset_list, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_reset_ipin;
CONNECT1860 C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
// PSC connections with EDMA mem_map( through MIF_TO_FUNC)
CONNECT1861 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_mif_opin, 0x02350000, 0x02350FFF, -0x02350000;
CONNECT1862 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_mif_opin, 0x02350000, 0x02350FFF, -0x02350000;
CONNECT1863 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PSC.MT_MIF2SSI.memtr_mif_opin, 0x02350000, 0x02350FFF, -0x02350000;
CONNECT1864 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out0, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_102;
CONNECT1865 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out1, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_103;
CONNECT1866 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out8, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_104;
CONNECT1867 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out9, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_105;
CONNECT1868 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out16, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_106;
CONNECT1869 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out17, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_107;
CONNECT1870 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out24, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_108;
CONNECT1871 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out25, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.INTSEL_in_pin_109;
CONNECT1872 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out0, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_102;
CONNECT1873 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out1, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_103;
CONNECT1874 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out8, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_104;
CONNECT1875 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out9, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_105;
CONNECT1876 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out16, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_106;
CONNECT1877 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out17, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_107;
CONNECT1878 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out24, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_108;
CONNECT1879 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out25, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.INTSEL_in_pin_109;
CONNECT1880 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out0, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_102;
CONNECT1881 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out1, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_103;
CONNECT1882 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out8, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_104;
CONNECT1883 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out9, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_105;
CONNECT1884 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out16, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_106;
CONNECT1885 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out17, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_107;
CONNECT1886 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out24, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_108;
CONNECT1887 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out25, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.INTSEL_in_pin_109;
CONNECT1888 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out0, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_102;
CONNECT1889 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out1, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_103;
CONNECT1890 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out8, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_104;
CONNECT1891 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out9, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_105;
CONNECT1892 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out16, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_106;
CONNECT1893 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out17, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_107;
CONNECT1894 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out24, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_108;
CONNECT1895 C66XX_S.SHARED_SYSTEM.CP_INTC0.cp_intc_out25, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.INTSEL_in_pin_109;
CONNECT1896 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out0, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_102;
CONNECT1897 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out1, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_103;
CONNECT1898 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out8, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_104;
CONNECT1899 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out9, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_105;
CONNECT1900 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out16, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_106;
CONNECT1901 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out17, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_107;
CONNECT1902 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out24, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_108;
CONNECT1903 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out25, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.INTSEL_in_pin_109;
CONNECT1904 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out0, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_102;
CONNECT1905 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out1, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_103;
CONNECT1906 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out8, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_104;
CONNECT1907 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out9, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_105;
CONNECT1908 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out16, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_106;
CONNECT1909 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out17, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_107;
CONNECT1910 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out24, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_108;
CONNECT1911 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out25, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.INTSEL_in_pin_109;
CONNECT1912 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out0, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_102;
CONNECT1913 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out1, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_103;
CONNECT1914 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out8, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_104;
CONNECT1915 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out9, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_105;
CONNECT1916 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out16, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_106;
CONNECT1917 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out17, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_107;
CONNECT1918 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out24, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_108;
CONNECT1919 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out25, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.INTSEL_in_pin_109;
CONNECT1920 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out0, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_102;
CONNECT1921 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out1, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_103;
CONNECT1922 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out8, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_104;
CONNECT1923 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out9, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_105;
CONNECT1924 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out16, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_106;
CONNECT1925 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out17, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_107;
CONNECT1926 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out24, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_108;
CONNECT1927 C66XX_S.SHARED_SYSTEM.CP_INTC1.cp_intc_out25, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.INTSEL_in_pin_109;
// SASS Connections
CONNECT1928 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x020C0000, 0x020CFFFF, -0x02000000;
CONNECT1929 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x020C0000, 0x020CFFFF, -0x02000000;
CONNECT1930 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x020C0000, 0x020CFFFF, -0x02000000;
CONNECT1931 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MIF_TO_FUNC_PASS.MT_MIF2SSI.memtr_mif_opin, 0x020C0000, 0x020CFFFF, -0x02000000;
// L1/L2 connections with MSMC mem_map
CONNECT1932 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10800000, 0x1087FFFF, -0x10000000; //L2
CONNECT1933 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10E00000, 0x10E07FFF, -0x10000000; //L1P
CONNECT1934 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_slave_mif, 0x10F00000, 0x10F07FFF, -0x10000000; //L1D
CONNECT1935 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11800000, 0x1187FFFF, -0x11000000; //L2
CONNECT1936 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11E00000, 0x11E07FFF, -0x11000000; //L1P
CONNECT1937 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_slave_mif, 0x11F00000, 0x11F07FFF, -0x11000000; //L1D
CONNECT1938 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12800000, 0x1287FFFF, -0x12000000; //L2
CONNECT1939 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12E00000, 0x12E07FFF, -0x12000000; //L1P
CONNECT1940 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_slave_mif, 0x12F00000, 0x12F07FFF, -0x12000000; //L1D
CONNECT1941 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13800000, 0x1387FFFF, -0x13000000; //L2
CONNECT1942 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13E00000, 0x13E07FFF, -0x13000000; //L1P
CONNECT1943 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_slave_mif, 0x13F00000, 0x13F07FFF, -0x13000000; //L1D
CONNECT1944 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14800000, 0x1487FFFF, -0x14000000; //L2
CONNECT1945 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14E00000, 0x14E07FFF, -0x14000000; //L1P
CONNECT1946 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_slave_mif, 0x14F00000, 0x14F07FFF, -0x14000000; //L1D
CONNECT1947 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15800000, 0x1587FFFF, -0x15000000; //L2
CONNECT1948 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15E00000, 0x15E07FFF, -0x15000000; //L1P
CONNECT1949 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_slave_mif, 0x15F00000, 0x15F07FFF, -0x15000000; //L1D
CONNECT1950 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16800000, 0x1687FFFF, -0x16000000; //L2
CONNECT1951 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16E00000, 0x16E07FFF, -0x16000000; //L1P
CONNECT1952 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_slave_mif, 0x16F00000, 0x16F07FFF, -0x16000000; //L1D
CONNECT1953 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17800000, 0x1787FFFF, -0x17000000; //L2
CONNECT1954 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17E00000, 0x17E07FFF, -0x17000000; //L1P
CONNECT1955 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_slave_mif, 0x17F00000, 0x17F07FFF, -0x17000000; //L1D
// L1D and L1P connection for CGEM program path
CONNECT1956 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1957 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1958 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1959 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1960 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1961 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1962 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1963 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7.prog_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1964 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1965 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1966 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1967 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1968 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1969 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1970 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1971 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7.prog_mem_map, 0x00F00000, 0x00F07FFF, 0;
// L1D and L1P connection for CGEM Data path
CONNECT1972 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1973 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1974 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1975 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1976 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1977 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1978 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1979 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0x00E00000, 0x00E07FFF, 0;
CONNECT1980 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1981 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1982 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1983 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1984 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1985 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1986 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, 0x00F00000, 0x00F07FFF, 0;
CONNECT1987 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.cgem_l1RAM_mif, C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, 0x00F00000, 0x00F07FFF, 0;
// Tag Ram connections
CONNECT1988 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_0.CPU0dmc_tag_ram_read;
CONNECT1989 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_0.CPU0pmc_tag_ram_read;
CONNECT1990 C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_0.CPU0umc_tag_ram_read;
CONNECT1991 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_1.CPU1dmc_tag_ram_read;
CONNECT1992 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_1.CPU1pmc_tag_ram_read;
CONNECT1993 C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_1.CPU1umc_tag_ram_read;
CONNECT1994 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_2.CPU2dmc_tag_ram_read;
CONNECT1995 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_2.CPU2pmc_tag_ram_read;
CONNECT1996 C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_2.CPU2umc_tag_ram_read;
CONNECT1997 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_3.CPU3dmc_tag_ram_read;
CONNECT1998 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_3.CPU3pmc_tag_ram_read;
CONNECT1999 C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_3.CPU3umc_tag_ram_read;
CONNECT2000 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_4.CPU4dmc_tag_ram_read;
CONNECT2001 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_4.CPU4pmc_tag_ram_read;
CONNECT2002 C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_4.CPU4umc_tag_ram_read;
CONNECT2003 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_5.CPU5dmc_tag_ram_read;
CONNECT2004 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_5.CPU5pmc_tag_ram_read;
CONNECT2005 C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_5.CPU5umc_tag_ram_read;
CONNECT2006 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_6.CPU6dmc_tag_ram_read;
CONNECT2007 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_6.CPU6pmc_tag_ram_read;
CONNECT2008 C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_6.CPU6umc_tag_ram_read;
CONNECT2009 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.dmc_tag_ram_read, C66XX_S.CPU_SYSTEM_7.CPU7dmc_tag_ram_read;
CONNECT2010 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.pmc_tag_ram_read, C66XX_S.CPU_SYSTEM_7.CPU7pmc_tag_ram_read;
CONNECT2011 C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.umc_tag_ram_read, C66XX_S.CPU_SYSTEM_7.CPU7umc_tag_ram_read;
// Memory Viewer Connections
//! For CPU0
CONNECT2012 C66XX_S.CPU_SYSTEM_0.CPU0l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1D_cache_dbg_read;
CONNECT2013 C66XX_S.CPU_SYSTEM_0.CPU0l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1D_cache_dbg_write;
CONNECT2014 C66XX_S.CPU_SYSTEM_0.CPU0l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1D_sram_dbg_read;
CONNECT2015 C66XX_S.CPU_SYSTEM_0.CPU0l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1D_sram_dbg_write;
CONNECT2016 C66XX_S.CPU_SYSTEM_0.CPU0l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1P_cache_dbg_read;
CONNECT2017 C66XX_S.CPU_SYSTEM_0.CPU0l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1P_cache_dbg_write;
CONNECT2018 C66XX_S.CPU_SYSTEM_0.CPU0l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1P_sram_dbg_read;
CONNECT2019 C66XX_S.CPU_SYSTEM_0.CPU0l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L1P_sram_dbg_write;
CONNECT2020 C66XX_S.CPU_SYSTEM_0.CPU0l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L2_cache_dbg_read;
CONNECT2021 C66XX_S.CPU_SYSTEM_0.CPU0l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L2_cache_dbg_write;
CONNECT2022 C66XX_S.CPU_SYSTEM_0.CPU0l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L2_sram_dbg_read;
CONNECT2023 C66XX_S.CPU_SYSTEM_0.CPU0l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.L2_sram_dbg_write;
CONNECT2024 C66XX_S.CPU_SYSTEM_0.CPU0ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.EXTMEM_ext_dbg_read;
CONNECT2025 C66XX_S.CPU_SYSTEM_0.CPU0ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_0.CGEM_SSI_0.EXTMEM_ext_dbg_write;
//! For CPU1
CONNECT2026 C66XX_S.CPU_SYSTEM_1.CPU1l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1D_cache_dbg_read;
CONNECT2027 C66XX_S.CPU_SYSTEM_1.CPU1l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1D_cache_dbg_write;
CONNECT2028 C66XX_S.CPU_SYSTEM_1.CPU1l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1D_sram_dbg_read;
CONNECT2029 C66XX_S.CPU_SYSTEM_1.CPU1l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1D_sram_dbg_write;
CONNECT2030 C66XX_S.CPU_SYSTEM_1.CPU1l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1P_cache_dbg_read;
CONNECT2031 C66XX_S.CPU_SYSTEM_1.CPU1l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1P_cache_dbg_write;
CONNECT2032 C66XX_S.CPU_SYSTEM_1.CPU1l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1P_sram_dbg_read;
CONNECT2033 C66XX_S.CPU_SYSTEM_1.CPU1l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L1P_sram_dbg_write;
CONNECT2034 C66XX_S.CPU_SYSTEM_1.CPU1l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L2_cache_dbg_read;
CONNECT2035 C66XX_S.CPU_SYSTEM_1.CPU1l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L2_cache_dbg_write;
CONNECT2036 C66XX_S.CPU_SYSTEM_1.CPU1l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L2_sram_dbg_read;
CONNECT2037 C66XX_S.CPU_SYSTEM_1.CPU1l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.L2_sram_dbg_write;
CONNECT2038 C66XX_S.CPU_SYSTEM_1.CPU1ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.EXTMEM_ext_dbg_read;
CONNECT2039 C66XX_S.CPU_SYSTEM_1.CPU1ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_1.CGEM_SSI_1.EXTMEM_ext_dbg_write;
//! For CPU2
CONNECT2040 C66XX_S.CPU_SYSTEM_2.CPU2l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1D_cache_dbg_read;
CONNECT2041 C66XX_S.CPU_SYSTEM_2.CPU2l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1D_cache_dbg_write;
CONNECT2042 C66XX_S.CPU_SYSTEM_2.CPU2l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1D_sram_dbg_read;
CONNECT2043 C66XX_S.CPU_SYSTEM_2.CPU2l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1D_sram_dbg_write;
CONNECT2044 C66XX_S.CPU_SYSTEM_2.CPU2l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1P_cache_dbg_read;
CONNECT2045 C66XX_S.CPU_SYSTEM_2.CPU2l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1P_cache_dbg_write;
CONNECT2046 C66XX_S.CPU_SYSTEM_2.CPU2l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1P_sram_dbg_read;
CONNECT2047 C66XX_S.CPU_SYSTEM_2.CPU2l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L1P_sram_dbg_write;
CONNECT2048 C66XX_S.CPU_SYSTEM_2.CPU2l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L2_cache_dbg_read;
CONNECT2049 C66XX_S.CPU_SYSTEM_2.CPU2l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L2_cache_dbg_write;
CONNECT2050 C66XX_S.CPU_SYSTEM_2.CPU2l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L2_sram_dbg_read;
CONNECT2051 C66XX_S.CPU_SYSTEM_2.CPU2l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.L2_sram_dbg_write;
CONNECT2052 C66XX_S.CPU_SYSTEM_2.CPU2ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.EXTMEM_ext_dbg_read;
CONNECT2053 C66XX_S.CPU_SYSTEM_2.CPU2ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_2.CGEM_SSI_2.EXTMEM_ext_dbg_write;
//! For CPU3
CONNECT2054 C66XX_S.CPU_SYSTEM_3.CPU3l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1D_cache_dbg_read;
CONNECT2055 C66XX_S.CPU_SYSTEM_3.CPU3l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1D_cache_dbg_write;
CONNECT2056 C66XX_S.CPU_SYSTEM_3.CPU3l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1D_sram_dbg_read;
CONNECT2057 C66XX_S.CPU_SYSTEM_3.CPU3l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1D_sram_dbg_write;
CONNECT2058 C66XX_S.CPU_SYSTEM_3.CPU3l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1P_cache_dbg_read;
CONNECT2059 C66XX_S.CPU_SYSTEM_3.CPU3l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1P_cache_dbg_write;
CONNECT2060 C66XX_S.CPU_SYSTEM_3.CPU3l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1P_sram_dbg_read;
CONNECT2061 C66XX_S.CPU_SYSTEM_3.CPU3l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L1P_sram_dbg_write;
CONNECT2062 C66XX_S.CPU_SYSTEM_3.CPU3l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L2_cache_dbg_read;
CONNECT2063 C66XX_S.CPU_SYSTEM_3.CPU3l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L2_cache_dbg_write;
CONNECT2064 C66XX_S.CPU_SYSTEM_3.CPU3l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L2_sram_dbg_read;
CONNECT2065 C66XX_S.CPU_SYSTEM_3.CPU3l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.L2_sram_dbg_write;
CONNECT2066 C66XX_S.CPU_SYSTEM_3.CPU3ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.EXTMEM_ext_dbg_read;
CONNECT2067 C66XX_S.CPU_SYSTEM_3.CPU3ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_3.CGEM_SSI_3.EXTMEM_ext_dbg_write;
//! For CPU4
CONNECT2068 C66XX_S.CPU_SYSTEM_4.CPU4l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1D_cache_dbg_read;
CONNECT2069 C66XX_S.CPU_SYSTEM_4.CPU4l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1D_cache_dbg_write;
CONNECT2070 C66XX_S.CPU_SYSTEM_4.CPU4l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1D_sram_dbg_read;
CONNECT2071 C66XX_S.CPU_SYSTEM_4.CPU4l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1D_sram_dbg_write;
CONNECT2072 C66XX_S.CPU_SYSTEM_4.CPU4l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1P_cache_dbg_read;
CONNECT2073 C66XX_S.CPU_SYSTEM_4.CPU4l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1P_cache_dbg_write;
CONNECT2074 C66XX_S.CPU_SYSTEM_4.CPU4l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1P_sram_dbg_read;
CONNECT2075 C66XX_S.CPU_SYSTEM_4.CPU4l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L1P_sram_dbg_write;
CONNECT2076 C66XX_S.CPU_SYSTEM_4.CPU4l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L2_cache_dbg_read;
CONNECT2077 C66XX_S.CPU_SYSTEM_4.CPU4l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L2_cache_dbg_write;
CONNECT2078 C66XX_S.CPU_SYSTEM_4.CPU4l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L2_sram_dbg_read;
CONNECT2079 C66XX_S.CPU_SYSTEM_4.CPU4l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.L2_sram_dbg_write;
CONNECT2080 C66XX_S.CPU_SYSTEM_4.CPU4ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.EXTMEM_ext_dbg_read;
CONNECT2081 C66XX_S.CPU_SYSTEM_4.CPU4ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_4.CGEM_SSI_4.EXTMEM_ext_dbg_write;
//! For CPU5
CONNECT2082 C66XX_S.CPU_SYSTEM_5.CPU5l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1D_cache_dbg_read;
CONNECT2083 C66XX_S.CPU_SYSTEM_5.CPU5l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1D_cache_dbg_write;
CONNECT2084 C66XX_S.CPU_SYSTEM_5.CPU5l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1D_sram_dbg_read;
CONNECT2085 C66XX_S.CPU_SYSTEM_5.CPU5l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1D_sram_dbg_write;
CONNECT2086 C66XX_S.CPU_SYSTEM_5.CPU5l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1P_cache_dbg_read;
CONNECT2087 C66XX_S.CPU_SYSTEM_5.CPU5l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1P_cache_dbg_write;
CONNECT2088 C66XX_S.CPU_SYSTEM_5.CPU5l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1P_sram_dbg_read;
CONNECT2089 C66XX_S.CPU_SYSTEM_5.CPU5l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L1P_sram_dbg_write;
CONNECT2090 C66XX_S.CPU_SYSTEM_5.CPU5l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L2_cache_dbg_read;
CONNECT2091 C66XX_S.CPU_SYSTEM_5.CPU5l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L2_cache_dbg_write;
CONNECT2092 C66XX_S.CPU_SYSTEM_5.CPU5l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L2_sram_dbg_read;
CONNECT2093 C66XX_S.CPU_SYSTEM_5.CPU5l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.L2_sram_dbg_write;
CONNECT2094 C66XX_S.CPU_SYSTEM_5.CPU5ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.EXTMEM_ext_dbg_read;
CONNECT2095 C66XX_S.CPU_SYSTEM_5.CPU5ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_5.CGEM_SSI_5.EXTMEM_ext_dbg_write;
//! For CPU6
CONNECT2096 C66XX_S.CPU_SYSTEM_6.CPU6l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1D_cache_dbg_read;
CONNECT2097 C66XX_S.CPU_SYSTEM_6.CPU6l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1D_cache_dbg_write;
CONNECT2098 C66XX_S.CPU_SYSTEM_6.CPU6l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1D_sram_dbg_read;
CONNECT2099 C66XX_S.CPU_SYSTEM_6.CPU6l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1D_sram_dbg_write;
CONNECT2100 C66XX_S.CPU_SYSTEM_6.CPU6l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1P_cache_dbg_read;
CONNECT2101 C66XX_S.CPU_SYSTEM_6.CPU6l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1P_cache_dbg_write;
CONNECT2102 C66XX_S.CPU_SYSTEM_6.CPU6l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1P_sram_dbg_read;
CONNECT2103 C66XX_S.CPU_SYSTEM_6.CPU6l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L1P_sram_dbg_write;
CONNECT2104 C66XX_S.CPU_SYSTEM_6.CPU6l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L2_cache_dbg_read;
CONNECT2105 C66XX_S.CPU_SYSTEM_6.CPU6l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L2_cache_dbg_write;
CONNECT2106 C66XX_S.CPU_SYSTEM_6.CPU6l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L2_sram_dbg_read;
CONNECT2107 C66XX_S.CPU_SYSTEM_6.CPU6l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.L2_sram_dbg_write;
CONNECT2108 C66XX_S.CPU_SYSTEM_6.CPU6ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.EXTMEM_ext_dbg_read;
CONNECT2109 C66XX_S.CPU_SYSTEM_6.CPU6ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_6.CGEM_SSI_6.EXTMEM_ext_dbg_write;
//! For CPU7
CONNECT2110 C66XX_S.CPU_SYSTEM_7.CPU7l1d_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1D_cache_dbg_read;
CONNECT2111 C66XX_S.CPU_SYSTEM_7.CPU7l1d_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1D_cache_dbg_write;
CONNECT2112 C66XX_S.CPU_SYSTEM_7.CPU7l1d_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1D_sram_dbg_read;
CONNECT2113 C66XX_S.CPU_SYSTEM_7.CPU7l1d_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1D_sram_dbg_write;
CONNECT2114 C66XX_S.CPU_SYSTEM_7.CPU7l1p_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1P_cache_dbg_read;
CONNECT2115 C66XX_S.CPU_SYSTEM_7.CPU7l1p_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1P_cache_dbg_write;
CONNECT2116 C66XX_S.CPU_SYSTEM_7.CPU7l1p_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1P_sram_dbg_read;
CONNECT2117 C66XX_S.CPU_SYSTEM_7.CPU7l1p_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L1P_sram_dbg_write;
CONNECT2118 C66XX_S.CPU_SYSTEM_7.CPU7l2_cache_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L2_cache_dbg_read;
CONNECT2119 C66XX_S.CPU_SYSTEM_7.CPU7l2_cache_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L2_cache_dbg_write;
CONNECT2120 C66XX_S.CPU_SYSTEM_7.CPU7l2_sram_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L2_sram_dbg_read;
CONNECT2121 C66XX_S.CPU_SYSTEM_7.CPU7l2_sram_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.L2_sram_dbg_write;
CONNECT2122 C66XX_S.CPU_SYSTEM_7.CPU7ext_mem_dbg_read_in, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.EXTMEM_ext_dbg_read;
CONNECT2123 C66XX_S.CPU_SYSTEM_7.CPU7ext_mem_dbg_write_out, C66XX_S.CPU_SYSTEM_7.CGEM_SSI_7.EXTMEM_ext_dbg_write;
//New - added for new QMSS interface and CDMA model changes
CONNECT2124 C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_read_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_read_ipin;
CONNECT2125 C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_write_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_write_ipin;
CONNECT2126 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT2127 C66XX_S.SHARED_SYSTEM.EDMA_0_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT2128 C66XX_S.SHARED_SYSTEM.EDMA_1_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT2129 C66XX_S.SHARED_SYSTEM.EDMA_2_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_mif_opin, 0x34000000, 0x34063000, -0x34000000;
CONNECT2130 C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_reset_ipin, System.SimBridge.global_reset_list;
CONNECT2131 C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.is_little_endian_ipin, C66XX_S.CPU_SYSTEM_0.CPU0_endianness;
CONNECT2132 C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_dbg_read_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_dbg_read_ipin;
CONNECT2133 C66XX_S.SHARED_SYSTEM.MEMTR_QM_DMA_Config.MT_MIF2SSI.memtr_dbg_write_opin, C66XX_S.SHARED_SYSTEM.QUEUE_MANAGER.qmss_dma_dbg_write_ipin;
CONNECT2134 C66XX_S.SHARED_SYSTEM.MSMC.msmc_mem_map, C66XX_S.SHARED_SYSTEM.MEMTR_QM_Config.MT_MIF2SSI.memtr_mif_opin, 0x02AB0000, 0x02AB1FFF, -0x02A00000;
END System;
// --- PDATS enablement -------------------//
SECTION PDATS_TRACE_ON_CORE0;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_0.CPU0_mem_map, System.C66XX_S.CPU_SYSTEM_0.CPU0.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE0;
SECTION PDATS_TRACE_ON_CORE1;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_1.CPU1_mem_map, System.C66XX_S.CPU_SYSTEM_1.CPU1.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE1;
SECTION PDATS_TRACE_ON_CORE2;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_2.CPU2_mem_map, System.C66XX_S.CPU_SYSTEM_2.CPU2.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE2;
SECTION PDATS_TRACE_ON_CORE3;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_3.CPU3_mem_map, System.C66XX_S.CPU_SYSTEM_3.CPU3.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE3;
SECTION PDATS_TRACE_ON_CORE4;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_4.CPU4_mem_map, System.C66XX_S.CPU_SYSTEM_4.CPU4.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE4;
SECTION PDATS_TRACE_ON_CORE5;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_5.CPU5_mem_map, System.C66XX_S.CPU_SYSTEM_5.CPU5.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE5;
SECTION PDATS_TRACE_ON_CORE6;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_6.CPU6_mem_map, System.C66XX_S.CPU_SYSTEM_6.CPU6.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE6;
SECTION PDATS_TRACE_ON_CORE7;
MODULE PDATS_TRACE;
ACCESS_SIZE_TRACE ON; // For Access width tracing
TIMESTAMP_WITH_MEMSTALLS OFF; // OFF -> The tracing would be w.r.t CPU cycles (no stalls)
MULTI_CORE ON;
END PDATS_TRACE;
CONNECT1 System.C66XX_S.CPU_SYSTEM_7.CPU7_mem_map, System.C66XX_S.CPU_SYSTEM_7.CPU7.cpu_pdats_mif, 0x0, 0xFFFFFFFF, 0;
END PDATS_TRACE_ON_CORE7;
// -------------------- END PDATS enablement -------------------//
//*****************************************************************************************************************************//
//
// As per following specs-
//
// chip_level_nysh.pdf VERSION 0.1.0
// interrupts_nysh.pdf VERSION 0.1.1
// ip_integration_nysh.pdf VERSION 0.1.0
// chip_config_nysh.pdf VERSION 0.1.0
// QM Queue assignment VERSION
//*****************************************************************************************************************************//
Hi Weihua,
did you solve your problem? I guess I have the same on
- C6670 Device Functional Simulator, Little Endian
- Linux Machine (Ubuntu 12.04.1 LTS (GNU/Linux 3.2.0-31-generic x86_64) )
I always get this warning :
TMS320C66x_0: Warning: Write operation not permitted since EDMA is disabled Read operation not permitted since EDMA is disabled ...
Anyone else with a solution?
Best Regards
Simon
Simon,
We will look into this issue. Somehow we are unable to reproduce this issue on existing edma testcases in our regression suite. I verified one of the edma cases now on windows also and it works. Is it possible for you send some .out that can reproduce this issue?
regards,
Sheshadri
Simon,
We loaded the .out you had shared on C6670 Device Functional Simulator, Little Endian on C66x_0 and found that the testcase completes without any EDMA messages. This is on CCS5.3 on ubuntu10 linux. It halts at abort label.
Below is the message we got on console...
[TMS320C66x_0] DSP Revision: Revision = 0x0000
Debug message - /home/schuberts/projekte/sdrnyq/branches/sync_module__test_project_simulator/src/board/board.c:260 (set_local_mac_and_ip_address)
Local MAC: 00:00:00:00:00:00
This is C6670 simulator
This is Board 0
This is DSP number 0
This is core number 0
The IP address of this DSP is: 0.0.0.0
The MAC address of this DSP is: 00:00:00:00:00:00
AIF2: Module Power Domain [ON]
****************************************************************************
EVM initialization done.
****************************************************************************
regards,
Sheshadri
please press "pause" to get the message
maybe it's useful to set an software breakpoint right before starting the edma process...i will investigate this.
regards,
simon
Sheshadri,
I investigated a bit and found, that the function EDMA3_DRV_create () leads to this warning ("Write operation not permitted since EDMA is disabled ...").
I use the file 'sample_init.c' , coming with the EDMA example. There the above function is called three times. the resulting "edma3Result" is never EDMA3_DRV_SOK.
I will send you an .out with a breakpoint right before calling the function, so you can step and see the warning.
Many thanks for your help,
Simon
Hi Simon,
Sorry I could not respond earlier. Even with the new .out you shared, I am unable to reproduce. Can you share the folder simulation_keystone1 inside <ccs installation>/.../ccs_base. You can zip this folder and share it with me. Will get back to you to see is I can reproduce with this,.
regards,
Sheshadri
