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OMAP3530--CCS V5.1 Disassembly Output

Other Parts Discussed in Thread: CCSTUDIO, OMAP3530

Dear Community,

I suspect I'm having a configuration problem with Code Composer, as some of the target address in the disassembly window view does not match target address for some instructions:

I am using CCStudio V5.1.  I cross compile my source using arm-angstrom-gcc for omap3530 Target.  I debug with xds560v2 target configuration, ARM Cortex A8, and I create an empty project.  I boot my application from the U-Boot.

This code does infinite test on global constant "wait_around" initialized to "1"

The assembler listing file looks like this:

.

.

247:main.c        ****     while(wait_around);^M
 920                    .loc 2 247 0
 921 05f0 14329FE5      ldr r3,.L70+16
 922 05f4 003093E5      ldr r3,[r3,#0]
 923 05f8 000053E3      cmp r3,#0
 924 05fc FBFFFF1A      bne .L57

The target address of "wait_around" in the map file is:

820be510 D wait_around

But in the CCS Disassembly window the code looks like this:

.

247           while(wait_around);
820009b0:   E59F3214 LDR             R3, 0x82000BCC <<<<<<
820009b4:   E5933000 LDR             R3, [R3]
820009b8:   E3530000 CMP             R3, #0
820009bc:   1AFFFFFB BNE             0x820009B0

Yet when I modify the symbol from the watch window, the correct address 820be510 appears. 

My question...on assembly address 0x820009b0 why does CCS show 0x82000BCC and not 0x820be510 for the target address of the LDR instruction?

  • I think 0x82000BCC is the address of a constant table entry embedded in the .text section, and this constant table entry contains the function address 0x820be510; please look at the disassembly for address 0x82000BCC to verify this.

  • Yes, that's exactly right.  The address of the constant "wait_around" is stored at the address 0x82000BEC.  So We load the address at which the address of the static is stored at, and then perform an indirect load followed by compare.

    244           while(wait_around);
    82000938:   E59F32AC LDR             R3, 0x82000BEC
    8200093c:   E5933000 LDR             R3, [R3]
    82000940:   E3530000 CMP             R3, #0
    82000944:   1AFFFFFB BNE             0x82000938

    Interesting that the compare instruction is required.  Why not just let the load of a 0 value effect the condition codes in CPSR?

    Thanks, regards

    E.T.

  • I'm not an ARM expert, but I don't think LDR sets CPSR.