Hi,
In Code Generation Tools FAQ: http://processors.wiki.ti.com/index.php/Code_Generation_Tools_FAQ#Q:_What_are_the_best_compiler_build_options.3F
It is mentioned that “I can ensure priority ordering of sections across chips with different internal memory sizes with 1 command file”
May I ask can I change the location of my SECTIONS across chips with 1 command file ?
For e.g in DSPC6678 I want for Core0 make data in MSMC, and for Core1..7 use DDR?
Can I do it with 1 command file ? and how ?