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Code Composer v3.3 Profile Clock Setup

Andrew Kiang
Prodigy 80 points


I have a simple question regarding the Profile Clock in Code Composer v3.3. I am using the OMAP L137 and Simulink to generate code for real time noise cancellation.

I want to measure the time it takes to run through an iteration of my code (it is an adaptive algorithm). From what I know, you do:

Time passed = cycles * (1/300MHz)

In the Clock Setup you can choose from: Cycles, CPU Execute Cycles, etc.

When I pick Cycles, I get cycles ranging in the 100,000s which translates to an unacceptable amount of latency.

When I pick CPU Execute Cycles, I get more reasonable cycles in the 1000s and below.

Which one do I choose to measure the the correct amount of cycles the DSP takes to execute the code?

  • 0
    TI__Guru**** 472151 points

    Andrew Kiang said:

    When I pick Cycles, I get cycles ranging in the 100,000s which translates to an unacceptable amount of latency.

    When I pick CPU Execute Cycles, I get more reasonable cycles in the 1000s and below.

    I believe 'CPU Execute Cycles' counts just CPU instruction execute cycles and cross bank and memory bank stalls while 'Cycles' counts everything that 'CPU Execute Cycles' count in addition to pipeline stalls, memory latency and any other system effects. Hence it makes sense for 'Cycles' to be a much larger value.

    Thanks

    ki

  • 0 in reply to Ki
    Prodigy 80 points

    Thank you for your answer. However, I am still confused. My main question is:

    -Do I multiply 'CPU Execute Cycles' or 'Cycles' by (1/300MHz) to get the latency?

    As an experiment, I tried running a simple ADC to DAC system (audio input just goes to output) with nothing else and used the profile clock to measure the time it took to do this processing.

    I am sampling at 8 kHz, and by theory the processing time must be less than the sampling period which is (1/8000) or 125 microseconds for a real time system.

    Using 'Cycles', I get cycles in the range of 40k to 100k which translates to 133 microseconds to 333 microseconds which is an unacceptable delay.

    Using 'CPU Execute Cycles', I get cycles in the 1000s which translates to a few (less than 30) microseconds and meets real time requirements.

    If selecting 'Cycles' will give me the correct amount of latency, then I do not understand how it is possible to make a real time system using this DSP board. Using just the ADC and a DAC will already cause an unacceptable delay, and adding any further processing will just make the delay worse. I have seen papers that use older boards with lower clock speeds to perform real time audio processing, so I cannot believe that this 300 MHz DSP board is too slow (assuming selecting 'Cycles' is the right option).

    Thank you for your insight.

  • 0 in reply to Andrew Kiang
    TI__Guru**** 472151 points

    Andrew Kiang said:
    If selecting 'Cycles' will give me the correct amount of latency, then I do not understand how it is possible to make a real time system using this DSP board. Using just the ADC and a DAC will already cause an unacceptable delay, and adding any further processing will just make the delay worse. I have seen papers that use older boards with lower clock speeds to perform real time audio processing, so I cannot believe that this 300 MHz DSP board is too slow (assuming selecting 'Cycles' is the right option).

    The issue is not the DSP but the whole system. It could be if you are running everything out of external memory and have to deal with memory latency which is the bottle neck. You can try placing parts of your code in internal RAM (if you have any). Profiling is used to find bottlenecks in your system so you can improve that. Sounds like you just did that (find some bottlenecks)

    ki

  • 0 in reply to Ki
    Prodigy 80 points

    Thanks for your reply.

    When I use Code Composer to 'Load Program', is the program not loaded onto the DSP's internal memory? How do I find out where my code is being placed?

    I am using Simulink to generate code for this board to avoid handwriting code. Could that be why the latency is so high? I would think not, since Simulink Embedded Coder supports many TI boards and there would be no reason to make realizing a real time system so difficult.

    Here is the simple ADC -> DAC audio system I made in Simulink:

    I do not understand how such a simple system can have such an unacceptable number of profile clock cycles.

    Would Simulink really generate code in such a way that makes the processing super inefficient??

    Thanks.

  • 0 in reply to Andrew Kiang
    TI__Guru**** 472151 points

    Andrew Kiang said:
    When I use Code Composer to 'Load Program', is the program not loaded onto the DSP's internal memory? How do I find out where my code is being placed?

    Not necessarily. CCS will read the symbolic information in your out file to figure out where to load it. It is the linker that allocates where your program gets loaded to memory (and from where to run from). You can control the placement of this code using a linker command file (*.cmd file).

    Linker command files are covered in detail in Section 7.5 of the Assembly language user's guide:

    http://www.ti.com/lit/ug/spru186w/spru186w.pdf

    A summary is mentioned here: http://processors.wiki.ti.com/index.php/Troubleshooting_CCS_-_Data_Verification_Errors#Code_Generation_Tools

    Andrew Kiang said:
    I am using Simulink to generate code for this board to avoid handwriting code. Could that be why the latency is so high? I would think not, since Simulink Embedded Coder supports many TI boards and there would be no reason to make realizing a real time system so difficult.

    Sorry, I have little experience with Simulink. That question may be best asked to Mathworks support.

    ki

  • 0 in reply to Ki
    Prodigy 80 points

    Hi again.

    I tried locating the linker command file for the simple ADC -> DAC project (its named 'AUDIOINOUT.cmd') and the entire contents were:

    /* Include DSP/BIOS generated linker command file */
    -l AUDIOINOUTcfg.cmd
    /* Allocation of the custom code and data sections */
    SECTIONS
    {
        .mw_isrambuff:     > IRAM
    }

    Does this mean all my code is located in the internal RAM (IRAM) of the DSP?

    Is the other command file generated by the DSP/BIOS 'AUDIOINOUTcfg.cmd' involved in placing parts of my code that have critical timing requirements? I do not believe I am using DSP/BIOS. All I am using is the 'Profile Clock' and the 'Watch Window' to watch variables.

    Thanks for all the help.

  • 0 in reply to Andrew Kiang
    TI__Guru**** 472151 points

    Andrew Kiang said:
    Does this mean all my code is located in the internal RAM (IRAM) of the DSP?

    It just means that the .mw_isrambuff section is in IRAM. Majority of code is usually some section called .text see where that is allocated.

    Andrew Kiang said:
    Is the other command file generated by the DSP/BIOS 'AUDIOINOUTcfg.cmd' involved in placing parts of my code that have critical timing requirements? I do not believe I am using DSP/BIOS

    look for a file with an extension of *.tcf. That is a BIOS config file.

  • 0 in reply to Ki
    Prodigy 80 points

    There are only 2 cmd files I see: 'AUDIOINOUT.cmd' and 'AUDIOINOUTcfg.cmd'. The comments in the 'AUDIOINOUT.cmd' file I posted earlier seemed to imply 'AUDIOINOUTcfg.cmd' was only used for DSP/BIOS related operations. Is this not the case? Are the 'AUDIOINOUTcfg.cmd' and .tcf BIOS config files related to things not DSP/BIOS?

    Am I using DSP/BIOS? I have never used anything from the DSP/BIOS section of the toolbar. (picture below)

    I can provide the contents of the 'AUDIOINOUTcfg.cmd' and the tcf file if that will help. I am just confused as to whether the DSP/BIOS generated cmd and tcf files would influence things like where my code is located, how the profile clock operates, and other things I do not think are DSP/BIOS related.

    Thanks.

  • 0 in reply to Andrew Kiang
    TI__Guru**** 472151 points

    You seem to be using BIOS. A "*.cfg.cmd" file is a command file generated by DSP/BIOS. If you were not using it, it would not get generated and be part of your project.

    Andrew Kiang said:
    Are the 'AUDIOINOUTcfg.cmd' and .tcf BIOS config files related to things not DSP/BIOS?

    Those are related to BIOS. A *.tcf file is a BIOS configuration file. If you double-click on it, it should launch the BIOS tcf graphical viewer

    Andrew Kiang said:
    Am I using DSP/BIOS? I have never used anything from the DSP/BIOS section of the toolbar. (picture below)

    Those menus are to use the BIOS debug analysis tools. You do not have to use them to use BIOS

    Andrew Kiang said:
    . I am just confused as to whether the DSP/BIOS generated cmd and tcf files would influence things like where my code is located, how the profile clock operates, and other things I do not think are DSP/BIOS related.

    Absolutely. You can configure memory placement via BIOS.

    It would be good to get more familiar with BIOS:

    http://processors.wiki.ti.com/index.php/Category:DSPBIOS

    Thanks

    ki

  • 0 in reply to Ki
    Prodigy 80 points

    Hello again. I will paste the contents of the *.tcf file at the end.

    I see a section commented as 'Compiler sections' and under that is 'TEXTSEG' among a lot of other segments which seem to be SDRAM (external memory).

    I assume simply changing 'SDRAM' to 'IRAM' would not work, as I already get numerous errors in related *.c files when trying to rebuild with this minor change. (I can post this if it will help)

    The links you provided earlier about the linker seem helpful but I am still a bit lost. Understanding how to write a linker file to configure memory placement will no doubt take some time for me. I am looking for guidance as to the most effective approach to placing memory. I have a few questions:

    What sections should I be aiming for to move into internal memory (just the .text?)?

    How much faster will this make my processing time (is it worth it)? Is configuring memory the best option I have for cutting down on the processing time?

    audioinout.tcf:

    var params = {
        clockRate: 300,
        catalogName: "ti.catalog.c6000",
        deviceName: "6747"
    };


    // Customize generic platform with parameters specified above
    utils.loadPlatform("ti.platforms.generic", params);
    // Set commonly used BIOS features
    bios.disableRealTimeAnalysis(prog);
    bios.disableRtdx(prog);
    bios.enableTskManager(prog);
    bios.enableMemoryHeaps(prog);



    utils.importFile("C:/Program Files/MATLAB/R2012a/toolbox/target/extensions/processor/tic6000/src/tci/ecm.tci");
    // Set BIOS system timer to Timer 0, if available in this platform
    if (bios.CLK.TIMERSELECT != undefined) {
        var timerEnum = bios.CLK.TIMERSELECT$Enum();
        if (timerEnum.match("Timer\s0")) {
            bios.CLK.TIMERSELECT = "Timer 0";
        }
    }

    // Reset BIOS timer when opening
    if (bios.CLK.RESETTIMER != undefined) {
        bios.CLK.RESETTIMER = true;
    }

    var mem_seg;
    // Create memory segment for IRAM
    mem_seg = bios.MEM.instance("IRAM");
    if (mem_seg == null) {
        mem_seg = bios.MEM.create("IRAM");
    };
    if (mem_seg.createHeap != 0) {
    mem_seg.createHeap = 0;
    }
    mem_seg.space = "code/data";
    mem_seg.base = 0x11800000;
    mem_seg.len = 0x20000;

    // Create memory segment for L3_CBA_RAM
    mem_seg = bios.MEM.instance("L3_CBA_RAM");
    if (mem_seg == null) {
        mem_seg = bios.MEM.create("L3_CBA_RAM");
    };
    if (mem_seg.createHeap != 0) {
    mem_seg.createHeap = 0;
    }
    mem_seg.space = "code/data";
    mem_seg.base = 0x80000000;
    mem_seg.len = 0x20000;

    // Create memory segment for SDRAM
    mem_seg = bios.MEM.instance("SDRAM");
    if (mem_seg == null) {
        mem_seg = bios.MEM.create("SDRAM");
    };
    if (mem_seg.createHeap != 1) {
    mem_seg.createHeap = 1;
    }
    mem_seg.heapSize = 0x800000;
    mem_seg.enableHeapLabel = 1;
    mem_seg.heapLabel = prog.extern("SDRAM_HEAP");
    mem_seg.space = "code/data";
    mem_seg.base = 0xC0000000;
    mem_seg.len = 0x20000000;

    var DATAMEM = prog.module("MEM").instance("SDRAM");
    var CODEMEM = prog.module("MEM").instance("SDRAM");
    var HEAPMEM = prog.module("MEM").instance("SDRAM");
    bios.setMemCodeSections(prog, CODEMEM);
    bios.setMemDataNoHeapSections(prog, DATAMEM);
    bios.setMemDataHeapSections(prog, HEAPMEM);
    prog.module("MEM").BIOSSEG    = CODEMEM;
    prog.module("MEM").SYSINITSEG = CODEMEM;
    prog.module("MEM").TEXTSEG    = CODEMEM;
    // BIOSOBJ, MALLOCSEG and STACKSEG are read-only
    // when memory heaps are disabled
    if (bios.MEM.NOMEMORYHEAPS == false) {
        bios.MEM.BIOSOBJSEG = prog.get("MEM_NULL");
        bios.MEM.MALLOCSEG  = prog.get("MEM_NULL");
        bios.TSK.STACKSEG   = prog.get("MEM_NULL");
    }
    // Generate BIOS cache configuration
    bios.GBL.C64PLUSCONFIGURE = 1;
    bios.GBL.C64PLUSL1DCFG = "32k";
    bios.GBL.C64PLUSL1PCFG = "32k";
    bios.GBL.C64PLUSL2CFG  = "128k";
    // Mark SDRAM memory region (0xCFFF FFFF - 0xDFFF FFFF) as cache-able
    bios.GBL.C64PLUSMAR192to223 = 0xffffffff;

    // Mark shared RAM (0x8000 0000 - 0x80FF FFFF) as cache-able
    bios.GBL.C64PLUSMAR128to159 = 0x00000001;

    // Destroy zero size mem segment L1DSRAM if it exist
    var mem_seg = bios.MEM.instance("L1DSRAM");
    if (mem_seg != null) {
        mem_seg.destroy();
    };
    // Destroy zero size mem segment L1PSRAM if it exist
    var mem_seg = bios.MEM.instance("L1PSRAM");
    if (mem_seg != null) {
        mem_seg.destroy();
    };
    prog.module("GBL").ENDIANMODE = "little";
    prog.module("MEM").BIOSOBJSEG = prog.get("SDRAM");
    prog.module("MEM").MALLOCSEG = prog.get("SDRAM");
    prog.module("TSK").STACKSEG = prog.get("SDRAM");
    prog.module("MEM").STACKSIZE = 0x2000;
    //DSP/BIOS sections;
    prog.module("MEM").ARGSSEG = prog.get("IRAM");
    prog.module("MEM").GBLINITSEG = prog.get("IRAM");
    prog.module("MEM").TRCDATASEG = prog.get("IRAM");
    prog.module("MEM").SYSDATASEG = prog.get("IRAM");
    prog.module("MEM").OBJSEG = prog.get("IRAM");
    prog.module("MEM").BIOSSEG = prog.get("IRAM");
    prog.module("MEM").SYSINITSEG = prog.get("IRAM");
    prog.module("MEM").HWISEG = prog.get("IRAM");
    prog.module("MEM").HWIVECSEG = prog.get("IRAM");
    prog.module("MEM").RTDXTEXTSEG = prog.get("SDRAM");
    //Compiler sections;
    prog.module("MEM").TEXTSEG = prog.get("SDRAM");
    prog.module("MEM").SWITCHSEG = prog.get("SDRAM");
    prog.module("MEM").BSSSEG = prog.get("SDRAM");
    prog.module("MEM").FARSEG = prog.get("SDRAM");
    prog.module("MEM").CINITSEG = prog.get("SDRAM");
    prog.module("MEM").PINITSEG = prog.get("SDRAM");
    prog.module("MEM").CONSTSEG = prog.get("SDRAM");
    prog.module("MEM").DATASEG = prog.get("SDRAM");
    prog.module("MEM").CIOSEG = prog.get("SDRAM");
    prog.module("MEM").STACKSEG = prog.get("IRAM");
    prog.module("TSK").ENABLETSK = true;
    prog.module("TSK").OBJMEMSEG = prog.get("SDRAM");
    prog.module("TSK").instance("TSK_idle").order = 1;
    prog.module("TSK").instance("TSK_idle").stackMemSeg = prog.get("IRAM");
    prog.module("IDL").instance("LNK_dataPump").order = 1;
    prog.module("IDL").instance("RTA_dispatcher").order = 2;
    prog.module("IDL").instance("IDL_cpuLoad").order = 3;
    //Init/Terminate TSK.
    initTerminateTSK_TSK = prog.module("TSK").create("initTerminateTSK");
    initTerminateTSK_TSK.autoAllocateStack = true;
    initTerminateTSK_TSK.stackMemSeg = prog.get("IRAM");
    initTerminateTSK_TSK.stackSize = 4096;
    initTerminateTSK_TSK.fxn = prog.extern("initTerminateTSK_fcn", "C");
    initTerminateTSK_TSK.priority = 15;
    initTerminateTSK_TSK.order = 1;
    initTerminateTSK_TSK.comment = "Init/Terminate TSK.";
    //Base rate task.
    tBaseRateTSK_TSK = prog.module("TSK").create("tBaseRateTSK");
    tBaseRateTSK_TSK.autoAllocateStack = true;
    tBaseRateTSK_TSK.stackMemSeg = prog.get("IRAM");
    tBaseRateTSK_TSK.stackSize = 4096;
    tBaseRateTSK_TSK.fxn = prog.extern("tBaseRateTSK_fcn", "C");
    tBaseRateTSK_TSK.priority = 7;
    tBaseRateTSK_TSK.order = 1;
    tBaseRateTSK_TSK.comment = "Base rate task.";
    prog.module("SEM").OBJMEMSEG = prog.get("SDRAM");
    //Real-time clock semaphore.
    rtClockSEM = prog.module("SEM").create("rtClockSEM");
    rtClockSEM.comment = "Real-time clock semaphore.";
    //Stop semaphore.
    stopSEM = prog.module("SEM").create("stopSEM");
    stopSEM.comment = "Stop semaphore.";
    //Start semaphore.
    startSEM = prog.module("SEM").create("startSEM");
    startSEM.comment = "Start semaphore.";
    prog.module("SYS").EXITFXN = prog.extern("exitprocessing");
    //PRD module for timer interrupt and Ethernet
    bios.PRD.OBJMEMSEG = prog.get("SDRAM");
    bios.PRD.USECLK = true;
    timer1PRD       = bios.PRD.create("timer1PRD");
    timer1PRD.fxn   = prog.extern("Timer1_ISR");
    timer1PRD.arg0  = 1;
    timer1PRD.order = 1;
    bios.CLK.MICROSECONDS = 125;
    timer1PRD.period = 1;
    timer1PRD.comment = "Timer 1 ISR";
    prog.module("GBL").CALLUSERINITFXN = true;
    prog.module("GBL").USERINITFXN = prog.extern("targetInitialize");

    /*  Imported TCI files. */
    utils.importFile("C:/Program Files/MATLAB/R2012a/toolbox/target/extensions/processor/tic6000/blks/lct/src/c6747evm_aic31.tci");
    utils.importFile("C:/Program Files/MATLAB/R2012a/toolbox/target/extensions/processor/tic6000/blks/lct/src/c6747evm_i2c.tci");

    // !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
    if (config.hasReportedError == false) {
        prog.gen();
    }

  • 0 in reply to Andrew Kiang
    Prodigy 80 points

    Hi again.

    I have been fooling around with the Target Preferences block in Simulink which seems to have options to control where sections are placed in memory.

    I have placed all the sections I could select (.text, .cio, etc.) into IRAM. The only section I have been unable to place in IRAM is the .far section.

    I tested the Cycles per iteration of the simple audio ADC->DAC model and there was some improvement (from 40K-100K to now 30K-50K) which still does not meet the requirements for a real time system. Here is my question:

    Is there anything else I can do to make the processing faster?

    For reference I will paste a picture of the Simulink interface that controls memory placement the contents of the *.tcf file.

    var params = {
        clockRate: 300,
        catalogName: "ti.catalog.c6000",
        deviceName: "6747"
    };


    // Customize generic platform with parameters specified above
    utils.loadPlatform("ti.platforms.generic", params);
    // Set commonly used BIOS features
    bios.disableRealTimeAnalysis(prog);
    bios.disableRtdx(prog);
    bios.enableTskManager(prog);
    bios.enableMemoryHeaps(prog);



    utils.importFile("C:/Program Files/MATLAB/R2012a/toolbox/target/extensions/processor/tic6000/src/tci/ecm.tci");
    // Set BIOS system timer to Timer 0, if available in this platform
    if (bios.CLK.TIMERSELECT != undefined) {
        var timerEnum = bios.CLK.TIMERSELECT$Enum();
        if (timerEnum.match("Timer\s0")) {
            bios.CLK.TIMERSELECT = "Timer 0";
        }
    }

    // Reset BIOS timer when opening
    if (bios.CLK.RESETTIMER != undefined) {
        bios.CLK.RESETTIMER = true;
    }

    var mem_seg;
    // Create memory segment for IRAM
    mem_seg = bios.MEM.instance("IRAM");
    if (mem_seg == null) {
        mem_seg = bios.MEM.create("IRAM");
    };
    if (mem_seg.createHeap != 0) {
    mem_seg.createHeap = 0;
    }
    mem_seg.space = "code/data";
    mem_seg.base = 0x11800000;
    mem_seg.len = 0x30000;

    // Create memory segment for L3_CBA_RAM
    mem_seg = bios.MEM.instance("L3_CBA_RAM");
    if (mem_seg == null) {
        mem_seg = bios.MEM.create("L3_CBA_RAM");
    };
    if (mem_seg.createHeap != 0) {
    mem_seg.createHeap = 0;
    }
    mem_seg.space = "code/data";
    mem_seg.base = 0x80000000;
    mem_seg.len = 0x20000;

    // Create memory segment for SDRAM
    mem_seg = bios.MEM.instance("SDRAM");
    if (mem_seg == null) {
        mem_seg = bios.MEM.create("SDRAM");
    };
    if (mem_seg.createHeap != 1) {
    mem_seg.createHeap = 1;
    }
    mem_seg.heapSize = 0x800000;
    mem_seg.enableHeapLabel = 1;
    mem_seg.heapLabel = prog.extern("SDRAM_HEAP");
    mem_seg.space = "code/data";
    mem_seg.base = 0xC0000000;
    mem_seg.len = 0x10000000;

    var DATAMEM = prog.module("MEM").instance("IRAM");
    var CODEMEM = prog.module("MEM").instance("IRAM");
    var HEAPMEM = prog.module("MEM").instance("SDRAM");
    bios.setMemCodeSections(prog, CODEMEM);
    bios.setMemDataNoHeapSections(prog, DATAMEM);
    bios.setMemDataHeapSections(prog, HEAPMEM);
    prog.module("MEM").BIOSSEG    = CODEMEM;
    prog.module("MEM").SYSINITSEG = CODEMEM;
    prog.module("MEM").TEXTSEG    = CODEMEM;
    // BIOSOBJ, MALLOCSEG and STACKSEG are read-only
    // when memory heaps are disabled
    if (bios.MEM.NOMEMORYHEAPS == false) {
        bios.MEM.BIOSOBJSEG = prog.get("MEM_NULL");
        bios.MEM.MALLOCSEG  = prog.get("MEM_NULL");
        bios.TSK.STACKSEG   = prog.get("MEM_NULL");
    }
    // Generate BIOS cache configuration
    bios.GBL.C64PLUSCONFIGURE = 1;
    bios.GBL.C64PLUSL1DCFG = "32k";
    bios.GBL.C64PLUSL1PCFG = "32k";
    bios.GBL.C64PLUSL2CFG  = "64k";
    // Mark SDRAM memory region (0xCFFF FFFF - 0xDFFF FFFF) as cache-able
    bios.GBL.C64PLUSMAR192to223 = 0xffffffff;

    // Mark shared RAM (0x8000 0000 - 0x80FF FFFF) as cache-able
    bios.GBL.C64PLUSMAR128to159 = 0x00000001;

    // Destroy zero size mem segment L1DSRAM if it exist
    var mem_seg = bios.MEM.instance("L1DSRAM");
    if (mem_seg != null) {
        mem_seg.destroy();
    };
    // Destroy zero size mem segment L1PSRAM if it exist
    var mem_seg = bios.MEM.instance("L1PSRAM");
    if (mem_seg != null) {
        mem_seg.destroy();
    };
    prog.module("GBL").ENDIANMODE = "little";
    prog.module("MEM").BIOSOBJSEG = prog.get("SDRAM");
    prog.module("MEM").MALLOCSEG = prog.get("SDRAM");
    prog.module("TSK").STACKSEG = prog.get("SDRAM");
    prog.module("MEM").STACKSIZE = 0x2000;
    //DSP/BIOS sections;
    prog.module("MEM").ARGSSEG = prog.get("IRAM");
    prog.module("MEM").GBLINITSEG = prog.get("IRAM");
    prog.module("MEM").TRCDATASEG = prog.get("IRAM");
    prog.module("MEM").SYSDATASEG = prog.get("IRAM");
    prog.module("MEM").OBJSEG = prog.get("IRAM");
    prog.module("MEM").BIOSSEG = prog.get("IRAM");
    prog.module("MEM").SYSINITSEG = prog.get("IRAM");
    prog.module("MEM").HWISEG = prog.get("IRAM");
    prog.module("MEM").HWIVECSEG = prog.get("IRAM");
    prog.module("MEM").RTDXTEXTSEG = prog.get("IRAM");
    //Compiler sections;
    prog.module("MEM").TEXTSEG = prog.get("IRAM");
    prog.module("MEM").SWITCHSEG = prog.get("IRAM");
    prog.module("MEM").BSSSEG = prog.get("IRAM");
    prog.module("MEM").FARSEG = prog.get("L3_CBA_RAM");
    prog.module("MEM").CINITSEG = prog.get("IRAM");
    prog.module("MEM").PINITSEG = prog.get("IRAM");
    prog.module("MEM").CONSTSEG = prog.get("IRAM");
    prog.module("MEM").DATASEG = prog.get("IRAM");
    prog.module("MEM").CIOSEG = prog.get("IRAM");
    prog.module("MEM").STACKSEG = prog.get("IRAM");
    prog.module("TSK").ENABLETSK = true;
    prog.module("TSK").OBJMEMSEG = prog.get("IRAM");
    prog.module("TSK").instance("TSK_idle").order = 1;
    prog.module("TSK").instance("TSK_idle").stackMemSeg = prog.get("IRAM");
    prog.module("IDL").instance("LNK_dataPump").order = 1;
    prog.module("IDL").instance("RTA_dispatcher").order = 2;
    prog.module("IDL").instance("IDL_cpuLoad").order = 3;
    //Init/Terminate TSK.
    initTerminateTSK_TSK = prog.module("TSK").create("initTerminateTSK");
    initTerminateTSK_TSK.autoAllocateStack = true;
    initTerminateTSK_TSK.stackMemSeg = prog.get("IRAM");
    initTerminateTSK_TSK.stackSize = 4096;
    initTerminateTSK_TSK.fxn = prog.extern("initTerminateTSK_fcn", "C");
    initTerminateTSK_TSK.priority = 15;
    initTerminateTSK_TSK.order = 1;
    initTerminateTSK_TSK.comment = "Init/Terminate TSK.";
    //Base rate task.
    tBaseRateTSK_TSK = prog.module("TSK").create("tBaseRateTSK");
    tBaseRateTSK_TSK.autoAllocateStack = true;
    tBaseRateTSK_TSK.stackMemSeg = prog.get("IRAM");
    tBaseRateTSK_TSK.stackSize = 4096;
    tBaseRateTSK_TSK.fxn = prog.extern("tBaseRateTSK_fcn", "C");
    tBaseRateTSK_TSK.priority = 7;
    tBaseRateTSK_TSK.order = 1;
    tBaseRateTSK_TSK.comment = "Base rate task.";
    prog.module("SEM").OBJMEMSEG = prog.get("IRAM");
    //Real-time clock semaphore.
    rtClockSEM = prog.module("SEM").create("rtClockSEM");
    rtClockSEM.comment = "Real-time clock semaphore.";
    //Stop semaphore.
    stopSEM = prog.module("SEM").create("stopSEM");
    stopSEM.comment = "Stop semaphore.";
    //Start semaphore.
    startSEM = prog.module("SEM").create("startSEM");
    startSEM.comment = "Start semaphore.";
    prog.module("SYS").EXITFXN = prog.extern("exitprocessing");
    //PRD module for timer interrupt and Ethernet
    bios.PRD.OBJMEMSEG = prog.get("IRAM");
    bios.PRD.USECLK = true;
    timer1PRD       = bios.PRD.create("timer1PRD");
    timer1PRD.fxn   = prog.extern("Timer1_ISR");
    timer1PRD.arg0  = 1;
    timer1PRD.order = 1;
    bios.CLK.MICROSECONDS = 9.070295e+01;
    timer1PRD.period = 1;
    timer1PRD.comment = "Timer 1 ISR";
    prog.module("GBL").CALLUSERINITFXN = true;
    prog.module("GBL").USERINITFXN = prog.extern("targetInitialize");

    /*  Imported TCI files. */
    utils.importFile("C:/Program Files/MATLAB/R2012a/toolbox/target/extensions/processor/tic6000/blks/lct/src/c6747evm_aic31.tci");
    utils.importFile("C:/Program Files/MATLAB/R2012a/toolbox/target/extensions/processor/tic6000/blks/lct/src/c6747evm_i2c.tci");

    // !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
    if (config.hasReportedError == false) {
        prog.gen();
    }