I just installed then new version of CCS (5.3) in trying to solve the following problem which I had with a previous version of CCS. But I still got the same warnings after the program compiles.
In my sources files I have an assembly source file in which I define 3 sections using the .sect directive. The compiler will output 2 warnings #10247-D creating a section "section name" whithout SECTIONS and will map correctly the third one.
I looked out at the results of mapping in the "project.map" file and also in an output file " project.txt (TI-TXT format") to verify if something was inserted in the different sections.
The compiler inserts properly the codes in the 3 sections but the start address of 2 of them are not assigned correctly. It maps the first one at address 00 and and the second one at addres 0x0010. The third one is correctly mapped at address 0x17f0.
The 3 sections that we are focusing on are:
ZAERA
ZAREA_CODE
BSLSIG
Here is the contents of three files: the input file" lnk_cc430f5137.cmd" ,and the two output files "projectName.map" and "projectName.txt"
File : lnk_cc430f5137.cmd:
/******************************************************************************/
/* lnk_cc430f5137.cmd - LINKER COMMAND FILE FOR LINKING CC430F5137 PROGRAMS */
/* */
/* Usage: lnk430 <obj files...> -o <out file> -m <map file> lnk.cmd */
/* cl430 <src files...> -z -o <out file> -m <map file> lnk.cmd */
/* */
/*----------------------------------------------------------------------------*/
/* These linker options are for command line linking only. For IDE linking, */
/* you should set your linker options in Project Properties */
/* -c LINK USING C CONVENTIONS */
/* -stack 0x0100 SOFTWARE STACK SIZE */
/* -heap 0x0100 HEAP AREA SIZE */
/* */
/*----------------------------------------------------------------------------*/
/****************************************************************************/
/* SPECIFY THE SYSTEM MEMORY MAP */
/****************************************************************************/
MEMORY
{
SFR : origin = 0x0000, length = 0x0010
PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
ZAREA : origin = 0x1000, length = 0x0006
ZAREA_CODE : origin = 0x1006, length = 0x002A
BSLSIG : origin = 0x17F0, length = 0x0010
RAM : origin = 0x1C00, length = 0x0FFE
INFOA : origin = 0x1980, length = 0x0080
INFOB : origin = 0x1900, length = 0x0080
INFOC : origin = 0x1880, length = 0x0080
INFOD : origin = 0x1800, length = 0x0080
FLASH : origin = 0x8000, length = 0x7F80
INT00 : origin = 0xFF80, length = 0x0002
INT01 : origin = 0xFF82, length = 0x0002
INT02 : origin = 0xFF84, length = 0x0002
INT03 : origin = 0xFF86, length = 0x0002
INT04 : origin = 0xFF88, length = 0x0002
INT05 : origin = 0xFF8A, length = 0x0002
INT06 : origin = 0xFF8C, length = 0x0002
INT07 : origin = 0xFF8E, length = 0x0002
INT08 : origin = 0xFF90, length = 0x0002
INT09 : origin = 0xFF92, length = 0x0002
INT10 : origin = 0xFF94, length = 0x0002
INT11 : origin = 0xFF96, length = 0x0002
INT12 : origin = 0xFF98, length = 0x0002
INT13 : origin = 0xFF9A, length = 0x0002
INT14 : origin = 0xFF9C, length = 0x0002
INT15 : origin = 0xFF9E, length = 0x0002
INT16 : origin = 0xFFA0, length = 0x0002
INT17 : origin = 0xFFA2, length = 0x0002
INT18 : origin = 0xFFA4, length = 0x0002
INT19 : origin = 0xFFA6, length = 0x0002
INT20 : origin = 0xFFA8, length = 0x0002
INT21 : origin = 0xFFAA, length = 0x0002
INT22 : origin = 0xFFAC, length = 0x0002
INT23 : origin = 0xFFAE, length = 0x0002
INT24 : origin = 0xFFB0, length = 0x0002
INT25 : origin = 0xFFB2, length = 0x0002
INT26 : origin = 0xFFB4, length = 0x0002
INT27 : origin = 0xFFB6, length = 0x0002
INT28 : origin = 0xFFB8, length = 0x0002
INT29 : origin = 0xFFBA, length = 0x0002
INT30 : origin = 0xFFBC, length = 0x0002
INT31 : origin = 0xFFBE, length = 0x0002
INT32 : origin = 0xFFC0, length = 0x0002
INT33 : origin = 0xFFC2, length = 0x0002
INT34 : origin = 0xFFC4, length = 0x0002
INT35 : origin = 0xFFC6, length = 0x0002
INT36 : origin = 0xFFC8, length = 0x0002
INT37 : origin = 0xFFCA, length = 0x0002
INT38 : origin = 0xFFCC, length = 0x0002
INT39 : origin = 0xFFCE, length = 0x0002
INT40 : origin = 0xFFD0, length = 0x0002
INT41 : origin = 0xFFD2, length = 0x0002
INT42 : origin = 0xFFD4, length = 0x0002
INT43 : origin = 0xFFD6, length = 0x0002
INT44 : origin = 0xFFD8, length = 0x0002
INT45 : origin = 0xFFDA, length = 0x0002
INT46 : origin = 0xFFDC, length = 0x0002
INT47 : origin = 0xFFDE, length = 0x0002
INT48 : origin = 0xFFE0, length = 0x0002
INT49 : origin = 0xFFE2, length = 0x0002
INT50 : origin = 0xFFE4, length = 0x0002
INT51 : origin = 0xFFE6, length = 0x0002
INT52 : origin = 0xFFE8, length = 0x0002
INT53 : origin = 0xFFEA, length = 0x0002
INT54 : origin = 0xFFEC, length = 0x0002
INT55 : origin = 0xFFEE, length = 0x0002
INT56 : origin = 0xFFF0, length = 0x0002
INT57 : origin = 0xFFF2, length = 0x0002
INT58 : origin = 0xFFF4, length = 0x0002
INT59 : origin = 0xFFF6, length = 0x0002
INT60 : origin = 0xFFF8, length = 0x0002
INT61 : origin = 0xFFFA, length = 0x0002
INT62 : origin = 0xFFFC, length = 0x0002
RESET : origin = 0xFFFE, length = 0x0002
}
/****************************************************************************/
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
/****************************************************************************/
SECTIONS
{
.bss : {} > RAM /* GLOBAL & STATIC VARS */
.data : {} > RAM /* GLOBAL & STATIC VARS */
.sysmem : {} > RAM /* DYNAMIC MEMORY ALLOCATION AREA */
.stack : {} > RAM (HIGH) /* SOFTWARE SYSTEM STACK */
.text : {} > FLASH /* CODE */
.cinit : {} > FLASH /* INITIALIZATION TABLES */
.const : {} > FLASH /* CONSTANT DATA */
.cio : {} > RAM /* C I/O BUFFER */
.pinit : {} > FLASH /* C++ CONSTRUCTOR TABLES */
.init_array : {} > FLASH /* C++ CONSTRUCTOR TABLES */
.mspabi.exidx : {} > FLASH /* C++ CONSTRUCTOR TABLES */
.mspabi.extab : {} > FLASH /* C++ CONSTRUCTOR TABLES */
.infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
.infoB : {} > INFOB
.infoC : {} > INFOC
.infoD : {} > INFOD
/* MSP430 INTERRUPT VECTORS */
.int00 : {} > INT00
.int01 : {} > INT01
.int02 : {} > INT02
.int03 : {} > INT03
.int04 : {} > INT04
.int05 : {} > INT05
.int06 : {} > INT06
.int07 : {} > INT07
.int08 : {} > INT08
.int09 : {} > INT09
.int10 : {} > INT10
.int11 : {} > INT11
.int12 : {} > INT12
.int13 : {} > INT13
.int14 : {} > INT14
.int15 : {} > INT15
.int16 : {} > INT16
.int17 : {} > INT17
.int18 : {} > INT18
.int19 : {} > INT19
.int20 : {} > INT20
.int21 : {} > INT21
.int22 : {} > INT22
.int23 : {} > INT23
.int24 : {} > INT24
.int25 : {} > INT25
.int26 : {} > INT26
.int27 : {} > INT27
.int28 : {} > INT28
.int29 : {} > INT29
.int30 : {} > INT30
.int31 : {} > INT31
.int32 : {} > INT32
.int33 : {} > INT33
.int34 : {} > INT34
.int35 : {} > INT35
.int36 : {} > INT36
.int37 : {} > INT37
.int38 : {} > INT38
.int39 : {} > INT39
.int40 : {} > INT40
.int41 : {} > INT41
.int42 : {} > INT42
.int43 : {} > INT43
.int44 : {} > INT44
.int45 : {} > INT45
.int46 : {} > INT46
.int47 : {} > INT47
.int48 : {} > INT48
.int49 : {} > INT49
.int50 : {} > INT50
.int51 : {} > INT51
.int52 : {} > INT52
.int53 : {} > INT53
.int54 : {} > INT54
.int55 : {} > INT55
.int56 : {} > INT56
.int57 : {} > INT57
.int58 : {} > INT58
.int59 : {} > INT59
.int60 : {} > INT60
.int61 : {} > INT61
.int62 : {} > INT62
/* AES : { * ( .int45 ) } > INT45 type = VECT_INIT
RTC : { * ( .int46 ) } > INT46 type = VECT_INIT
.int47 : {} > INT47
PORT2 : { * ( .int48 ) } > INT48 type = VECT_INIT
PORT1 : { * ( .int49 ) } > INT49 type = VECT_INIT
TIMER1_A1 : { * ( .int50 ) } > INT50 type = VECT_INIT
TIMER1_A0 : { * ( .int51 ) } > INT51 type = VECT_INIT
DMA : { * ( .int52 ) } > INT52 type = VECT_INIT
CC1101 : { * ( .int53 ) } > INT53 type = VECT_INIT
TIMER0_A1 : { * ( .int54 ) } > INT54 type = VECT_INIT
TIMER0_A0 : { * ( .int55 ) } > INT55 type = VECT_INIT
ADC12 : { * ( .int56 ) } > INT56 type = VECT_INIT
USCI_B0 : { * ( .int57 ) } > INT57 type = VECT_INIT
USCI_A0 : { * ( .int58 ) } > INT58 type = VECT_INIT
WDT : { * ( .int59 ) } > INT59 type = VECT_INIT
COMP_B : { * ( .int60 ) } > INT60 type = VECT_INIT
UNMI : { * ( .int61 ) } > INT61 type = VECT_INIT
SYSNMI : { * ( .int62 ) } > INT62 type = VECT_INIT*/
.reset : {} > RESET /* MSP430 RESET VECTOR */
ZAERA : {} > ZAREA
ZAREA_CODE : {} > ZAREA_CODE
BSLSIG : {} > BSLSIG
}
/****************************************************************************/
/* INCLUDE PERIPHERALS MEMORY MAP */
/****************************************************************************/
-l cc430f5137.cmd
File : projectName.map (only the essential part of it)
******************************************************************************
MSP430 Linker PC v4.1.2
******************************************************************************
>> Linked Tue Apr 30 10:40:44 2013
OUTPUT FILE NAME: <Wireless_Update_Flash_based.out>
ENTRY POINT SYMBOL: "_c_int00" address: 0000873c
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
SFR 00000000 00000010 00000006 0000000a RWIX
PERIPHERALS_8BIT 00000010 000000f0 00000024 000000cc RWIX
PERIPHERALS_16BIT 00000100 00000100 00000000 00000100 RWIX
ZAREA 00001000 00000006 00000000 00000006 RWIX
ZAREA_CODE 00001006 0000002a 00000000 0000002a RWIX
BSL_CODE 00001030 0000007c 00000000 0000007c RWIX
BSLSIG 000017f0 00000010 00000010 00000000 RWIX
INFOD 00001800 00000080 00000000 00000080 RWIX
INFOC 00001880 00000080 00000000 00000080 RWIX
INFOB 00001900 00000080 00000000 00000080 RWIX
INFOA 00001980 00000080 00000000 00000080 RWIX
RAM 00001c00 00000ffe 0000018e 00000e70 RWIX
FLASH 00008000 00007f80 00000950 00007630 RWIX
INT00 0000ff80 00000002 00000000 00000002 RWIX
INT01 0000ff82 00000002 00000000 00000002 RWIX
INT02 0000ff84 00000002 00000000 00000002 RWIX
INT03 0000ff86 00000002 00000000 00000002 RWIX
INT04 0000ff88 00000002 00000000 00000002 RWIX
INT05 0000ff8a 00000002 00000000 00000002 RWIX
INT06 0000ff8c 00000002 00000000 00000002 RWIX
INT07 0000ff8e 00000002 00000000 00000002 RWIX
INT08 0000ff90 00000002 00000000 00000002 RWIX
INT09 0000ff92 00000002 00000000 00000002 RWIX
INT10 0000ff94 00000002 00000000 00000002 RWIX
INT11 0000ff96 00000002 00000000 00000002 RWIX
INT12 0000ff98 00000002 00000000 00000002 RWIX
INT13 0000ff9a 00000002 00000000 00000002 RWIX
INT14 0000ff9c 00000002 00000000 00000002 RWIX
INT15 0000ff9e 00000002 00000000 00000002 RWIX
INT16 0000ffa0 00000002 00000000 00000002 RWIX
INT17 0000ffa2 00000002 00000000 00000002 RWIX
INT18 0000ffa4 00000002 00000000 00000002 RWIX
INT19 0000ffa6 00000002 00000000 00000002 RWIX
INT20 0000ffa8 00000002 00000000 00000002 RWIX
INT21 0000ffaa 00000002 00000000 00000002 RWIX
INT22 0000ffac 00000002 00000000 00000002 RWIX
INT23 0000ffae 00000002 00000000 00000002 RWIX
INT24 0000ffb0 00000002 00000000 00000002 RWIX
INT25 0000ffb2 00000002 00000000 00000002 RWIX
INT26 0000ffb4 00000002 00000000 00000002 RWIX
INT27 0000ffb6 00000002 00000000 00000002 RWIX
INT28 0000ffb8 00000002 00000000 00000002 RWIX
INT29 0000ffba 00000002 00000000 00000002 RWIX
INT30 0000ffbc 00000002 00000000 00000002 RWIX
INT31 0000ffbe 00000002 00000000 00000002 RWIX
INT32 0000ffc0 00000002 00000000 00000002 RWIX
INT33 0000ffc2 00000002 00000000 00000002 RWIX
INT34 0000ffc4 00000002 00000000 00000002 RWIX
INT35 0000ffc6 00000002 00000000 00000002 RWIX
INT36 0000ffc8 00000002 00000000 00000002 RWIX
INT37 0000ffca 00000002 00000000 00000002 RWIX
INT38 0000ffcc 00000002 00000000 00000002 RWIX
INT39 0000ffce 00000002 00000000 00000002 RWIX
INT40 0000ffd0 00000002 00000000 00000002 RWIX
INT41 0000ffd2 00000002 00000000 00000002 RWIX
INT42 0000ffd4 00000002 00000000 00000002 RWIX
INT43 0000ffd6 00000002 00000000 00000002 RWIX
INT44 0000ffd8 00000002 00000000 00000002 RWIX
INT45 0000ffda 00000002 00000000 00000002 RWIX
INT46 0000ffdc 00000002 00000000 00000002 RWIX
INT47 0000ffde 00000002 00000000 00000002 RWIX
INT48 0000ffe0 00000002 00000000 00000002 RWIX
INT49 0000ffe2 00000002 00000000 00000002 RWIX
INT50 0000ffe4 00000002 00000000 00000002 RWIX
INT51 0000ffe6 00000002 00000000 00000002 RWIX
INT52 0000ffe8 00000002 00000000 00000002 RWIX
INT53 0000ffea 00000002 00000000 00000002 RWIX
INT54 0000ffec 00000002 00000000 00000002 RWIX
INT55 0000ffee 00000002 00000000 00000002 RWIX
INT56 0000fff0 00000002 00000000 00000002 RWIX
INT57 0000fff2 00000002 00000000 00000002 RWIX
INT58 0000fff4 00000002 00000000 00000002 RWIX
INT59 0000fff6 00000002 00000000 00000002 RWIX
INT60 0000fff8 00000002 00000000 00000002 RWIX
INT61 0000fffa 00000002 00000000 00000002 RWIX
INT62 0000fffc 00000002 00000000 00000002 RWIX
RESET 0000fffe 00000002 00000002 00000000 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.pinit 0 00008000 00000000 UNINITIALIZED
ZAREA 0 00000000 00000006
00000000 00000006 RFBSL_Low_Level_Init.obj (ZAREA)
ZAERA_CODE
* 0 00000010 00000024
00000010 00000024 RFBSL_Low_Level_Init.obj (ZAERA_CODE)
BSLSIG 0 000017f0 00000010
000017f0 00000010 RFBSL_Low_Level_Init.obj (BSLSIG)
.bss 0 00001c00 0000013e UNINITIALIZED
00001c00 0000012e wbsl.obj (.bss)
00001d2e 00000008 rts430x.lib : _lock.obj (.bss)
00001d36 00000008 : boot.obj (.bss)
.data 0 00001c00 00000000 UNINITIALIZED
.stack 0 00002bac 00000050 UNINITIALIZED
00002bac 00000002 rts430x.lib : boot.obj (.stack)
00002bae 0000004e --HOLE--
.text 0 00008000 0000087c
00008000 00000130 wbsl.obj (.text:wbsl_receivePackets)
00008130 000000c2 wbsl.obj (.text:RadioIsr_wbsl)
000081f2 00000090 rf1a.obj (.text:Strobe)
00008282 00000090 wbsl.obj (.text:transmitPacket)
00008312 0000008a wbsl.obj (.text:wbsl_writePacket)
0000839c 0000006e wbsl.obj (.text:wbsl_link)
0000840a 00000066 rf1a.obj (.text:WritePATable)
00008470 00000064 wbsl.obj (.text:start_wbsl)
000084d4 0000005e wbsl.obj (.text:init_Activator)
00008532 00000046 rts430x.lib : autoinit.obj (.text:_auto_init)
00008578 00000042 rf1a.obj (.text:WriteBurstReg)
000085ba 00000042 wbsl.obj (.text:wbsl_replyAck)
000085fc 0000003c radio.obj (.text:radio_reset)
00008638 00000038 rf1a.obj (.text:WriteSingleReg)
00008670 00000038 wbsl.obj (.text:wbsl_writeBytes)
000086a8 00000036 wbsl.obj (.text:main)
000086de 00000034 rf1a.obj (.text:ReadSingleReg)
00008712 0000002a radio.obj (.text:WriteSmartRFReg)
0000873c 0000002a rts430x.lib : boot.obj (.text:_isr:_c_int00_noexit)
00008766 00000020 radio.obj (.text:ReceiveOff)
00008786 0000001e wbsl.obj (.text:reset_wbsl)
000087a4 0000001a wbsl.obj (.text:init_watchButtons)
000087be 0000001a wbsl.obj (.text:wbsl_setTimer)
000087d8 00000016 radio.obj (.text:config_radio_wbsl)
000087ee 00000016 rts430x.lib : div16u.obj (.text)
00008804 00000016 : mult16_f5hw.obj (.text)
0000881a 00000014 : memset.obj (.text:memset)
0000882e 00000012 radio.obj (.text:ReceiveOn)
00008840 00000012 rts430x.lib : memcpy.obj (.text:memcpy)
00008852 00000010 wbsl.obj (.text:wbsl_resetTimer)
00008862 00000010 wbsl.obj (.text:wbsl_writeByte)
00008872 00000004 rts430x.lib : pre_init.obj (.text:_system_pre_init)
00008876 00000004 : exit.obj (.text:abort)
0000887a 00000002 : _lock.obj (.text:_nop)
.cinit 0 0000887c 0000007a
0000887c 00000078 wbsl.obj (.cinit)
000088f4 00000002 --HOLE-- [fill = 0]
.const 0 000088f6 0000005a
000088f6 0000005a radio.obj (.const:RF1A_REG_SMARTRF_SETTING)
.reset 0 0000fffe 00000002
0000fffe 00000002 rts430x.lib : boot.obj (.reset)
File : projectName.txt (only the essential part of it)
0F 3C FE 3F FF 3F
@0010
D0 B3 0B 02 03 28 B1 C0 F0 00 00 00 C0 43 FF 01
00 13 0C 43 B2 D0 03 80 82 01 B2 93 FE FF 01 20
2C D3 10 01
@17f0
FF FF 22 00 A5 3C 5A C3 FF FF 00 00 FF FF FF FF
@8000
0A 14 4A 43 D2 53 28 1D F2 90 05 00 28 1D 05 28
F2 40 20 00 1C 1D CC 0A 89 3C B0 13 2E 88 3C 40
00 40 B0 13 BE 87 06 3C B2 B0 00 02 32 0F 02 24
B0 13 30 81 92 B3 44 03 03 20 D2 93 1E 1D F4 23
B0 13 52 88 B0 13 66 87 D2 93 1E 1D 03 24 C2 93
29 1D 65 20 D2 93 1E 1D 68 20 C2 43 1E 1D 5E 42
08 1C 3F 40 80 00 5F FE 0A 1C D2 92 27 1D 0A 1C
5C 20 C2 93 29 1D 19 20 4F 93 05 20 4C 43 3D 43
B0 13 BA 85 52 3C C2 43 28 1D 5E 42 0B 1C 5F 42
0C 1C 47 18 0F 5F 0E 5F 82 4E 2A 1D 5C 43 3D 43
B0 13 BA 85 D2 43 29 1D 40 3C 4F 93 32 24 5E 42
0C 1C 5F 42 0B 1C 47 18 0F 5F 0E 5F 1E 92 2C 1D
21 20 B0 13 12 83 5C 93 06 24 4C 43 1D 42 2C 1D
B0 13 BA 85 2A 3C C2 43 28 1D 5C 43 1D 42 2C 1D
Also there some other important notes:
1) The project was imported in CCS v5.3 and was originated from a previous version of compiler.
2) I have tried to start a completely new project from scratch usign the CCS v5.3. The problem is even worst ,it does map at all the sections and put every thing at address 0x8000.
3) Originaly I had 4 sections defined and two of them were correctly mapped. In my trials I did remove a section and tried to reinstate it. It never came back again and the complier declared 3 warnings instead of 2.
