XDS100V1

Marada Naveen Kumar

Other Parts Discussed in Thread: SN74LVC2T45, SN74CBT3125

Hi,

I am studying xds100v1 schematic and wondering how the jtag signals coming after the fet switches got converted from 5v(ftdi I/O voltage) to 3.3v(jtag I/O voltage required for targets) ?

over 12 years ago

MaciejKucia over 12 years ago

Mastermind 7925 points

The answer is there: http://processors.wiki.ti.com/index.php/XDS100#Q:_What_device_voltages_are_supported_by_the_XDS100v1.3F

Regards,
Maciej

Marada Naveen Kumar over 12 years ago in reply to MaciejKucia

Intellectual 615 points

Thanks Maciej,

I am at clarity on the SN74LVC2T45 (U5) transceiver which converts 3.3v signals(jtag) to 5v.but i cant see how the fet switch array SN74CBT3125 (U3) can do the opposite- its inputs are at 5v ,Vcc at 4.3(assuming 3.3v target) ?

MaciejKucia over 12 years ago in reply to Marada Naveen Kumar

Mastermind 7925 points

I guess like this: http://ics.nxp.com/support/documents/interface/pdf/an97055.pdf 2.3.1 Description of the level shift operation.

Regards,
Maciej

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