Hello.
I have two questions about linker's scripts:
1. I would like to specify one or a few routines from the library to place them into specific section:
ramfuncs : { -lrts2800_ml.lib<boot.obj>(.text:_c_int00) }
I've read the spru513e.pdf and didn't find the answer.
Also, not all specified objects took place at the specified section as requested:
ramfuncs : { -lrts2800_ml.lib<ctype.obj>(.econst) -lrts2800_ml.lib<memcpy_ff.obj,ctype.obj,strtol.obj>(.text) } > RAMM0 PAGE = 0
.text : > PRAMH0 PAGE = 0
After the link, I will have only ctype.obj(.econst) and memcpy_ff.obj(.text) while the "ramfuncs" and "strobj.obj(.text)" goes to ".text" section.
2. I have a base FLASHed image with a driverlib set and some other functions burned into the flash. I would like to test another software that use the same functions from the flash to save a RAM memory and FLASH life cycle. I just need to change a minor main functions and run on top of API lived on the FLASH. I have two link scripts:
FLASH variants:
/*
// TI File $Revision: /main/2 $
// Checkin $Date: August 2, 2006 16:56:49 $
//###########################################################################
//
// FILE: 2808_RAM_lnk.cmd
//
// TITLE: Linker Command File For 2808 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 2808 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP281x_Headers\cmd
//
// For BIOS applications add: DSP280x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP280x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP280x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP280x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP280x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F2808
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2808 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1 and H0 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
/* -heap 0x400
-stack 0x200 */
MEMORY
{
PAGE 0 :
/* For this example, H0 is split between PAGE 0 and PAGE 1 */
/* BEGIN is used for the "boot to SARAM" bootloader mode */
RAMM0 : origin = 0x000002, length = 0x0003AE
PRAMH0 : origin = 0x3F8E00, length = 0x002800
RESET : origin = 0x3FFFC0, length = 0x000002
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
BOOTROM : origin = 0x3FF000, length = 0x000FC0
FLS1_RAML0 : origin = 0x008000, length = 0x000E00 /* on-chip FLASH */
FLS2_RAML0 : origin = 0x0003B0, length = 0x000050 /* on-chip FLASH */
// RAML0 : origin = 0x009600, length = 0x000200 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x003000 /* on-chip FLASH */
FLASHD_RAMFN : origin = 0x3EB000, length = 0x001000 /* on-chip FLASH */
C_INT00 : origin = 0x3EC000, length = 0x000080 /* on-chip FLASH for _c_int00 */
DRVLIB : origin = 0x3EC080, length = 0x000500
FLASHC : origin = 0x3EC580, length = 0x003A80 /* on-chip FLASH */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
PAGE 1 :
/* For this example, H0 is split between PAGE 0 and PAGE 1 */
BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */
RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */
DRAMH0 : origin = 0x3FB600, length = 0x000300
}
SECTIONS
{
c_int00 :
{
-lc_int.lib(.text)
} > C_INT00, PAGE = 0
driverlib :
{
-ldriverlib.lib(.econst)
-ldriverlib.lib(.text)
} > DRVLIB, PAGE = 0
Flash28_API:
{
-lFlash2808_API_V302.lib(.econst)
-lFlash2808_API_V302.lib(.text)
-lbufops.lib(.econst)
-lbufops.lib(.text)
-lstrtol.lib(.econst)
-lstrtol.lib(.text)
} LOAD = FLASHD,
RUN = FLS1_RAML0,
LOAD_START(_Flash28_API_LoadStart),
LOAD_END(_Flash28_API_LoadEnd),
RUN_START(_Flash28_API_RunStart),
PAGE = 0
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
.cinit : > FLASHC PAGE = 0
.pinit : > FLASHC, PAGE = 0
.text : > FLASHC PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD_RAMFN,
RUN = FLS2_RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHC PAGE = 0
.switch : > FLASHC PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > DRAMH0, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > BOOTROM, type = NOLOAD, PAGE = 0
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
/*
// TI File $Revision: /main/2 $
// Checkin $Date: August 2, 2006 16:56:49 $
//###########################################################################
//
// FILE: 2808_RAM_lnk.cmd
//
// TITLE: Linker Command File For 2808 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 2808 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP281x_Headers\cmd
//
// For BIOS applications add: DSP280x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP280x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP280x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP280x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP280x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F2808
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2808 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1 and H0 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
/* -heap 0x400
-stack 0x200 */
MEMORY
{
PAGE 0 :
/* For this example, H0 is split between PAGE 0 and PAGE 1 */
/* BEGIN is used for the "boot to SARAM" bootloader mode */
RAMM0 : origin = 0x000002, length = 0x0003AE
PRAMH0 : origin = 0x3F8E00, length = 0x002800
RESET : origin = 0x3FFFC0, length = 0x000002
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
BOOTROM : origin = 0x3FF000, length = 0x000FC0
FLS1_RAML0 : origin = 0x008000, length = 0x000E00 /* on-chip FLASH */
FLS2_RAML0 : origin = 0x0003B0, length = 0x000050 /* on-chip FLASH */
// RAML0 : origin = 0x009600, length = 0x000200 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x003000 /* on-chip FLASH */
FLASHD_RAMFN : origin = 0x3EB000, length = 0x001000 /* on-chip FLASH */
C_INT00 : origin = 0x3EC000, length = 0x000080 /* on-chip FLASH for _c_int00 */
DRVLIB : origin = 0x3EC080, length = 0x000500
FLASHC : origin = 0x3EC580, length = 0x003A80 /* on-chip FLASH */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
PAGE 1 :
/* For this example, H0 is split between PAGE 0 and PAGE 1 */
BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */
RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */
DRAMH0 : origin = 0x3FB600, length = 0x000300
}
SECTIONS
{
c_int00 :
{
-lrts2800_ml.lib<boot.obj>(.text)
-ldriverlib.lib<DSP280x_CodeStartBranch.obj>(.text)
} > C_INT00, PAGE = 0
driverlib :
{
-ldriverlib.lib(.econst)
-ldriverlib.lib(.text)
} > DRVLIB, PAGE = 0
Flash28_API:
{
-lFlash2808_API_V302.lib(.econst)
-lFlash2808_API_V302.lib(.text)
-lrts2800_ml.lib<memset.obj>(.text)
-lrts2800_ml.lib<memcpy_ff.obj>(.text)
-lrts2800_ml.lib<strtol.obj>(.text)
-lrts2800_ml.lib<ctype.obj>(.econst)
-lbufops.lib(.econst)
-lbufops.lib(.text)
} LOAD = FLASHD,
RUN = FLS1_RAML0,
LOAD_START(_Flash28_API_LoadStart),
LOAD_END(_Flash28_API_LoadEnd),
RUN_START(_Flash28_API_RunStart),
PAGE = 0
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
.cinit : > FLASHC PAGE = 0
.pinit : > FLASHC, PAGE = 0
.text : > FLASHC PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD_RAMFN,
RUN = FLS2_RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHC PAGE = 0
.switch : > FLASHC PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > DRAMH0, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > BOOTROM, type = NOLOAD, PAGE = 0
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
RAM variant:
/*
// TI File $Revision: /main/2 $
// Checkin $Date: August 2, 2006 16:56:49 $
//###########################################################################
//
// FILE: 2808_RAM_lnk.cmd
//
// TITLE: Linker Command File For 2808 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 2808 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP281x_Headers\cmd
//
// For BIOS applications add: DSP280x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP280x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP280x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP280x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP280x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F2808
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2808 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1 and H0 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
/* -heap 0x400
-stack 0x200 */
MEMORY
{
PAGE 0 :
/* For this example, H0 is split between PAGE 0 and PAGE 1 */
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000002, length = 0x0003AE
PRAMH0 : origin = 0x3F8E00, length = 0x002B00
RESET : origin = 0x3FFFC0, length = 0x000002
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
BOOTROM : origin = 0x3FF000, length = 0x000FC0
FLS1_RAML0 : origin = 0x008000, length = 0x000E00 /* on-chip FLASH */
FLS2_RAML0 : origin = 0x0003B0, length = 0x000050 /* on-chip FLASH */
// RAML0 : origin = 0x009600, length = 0x000200 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x003000 /* on-chip FLASH */
FLASHD_RAMFN : origin = 0x3EB000, length = 0x001000 /* on-chip FLASH */
C_INT00 : origin = 0x3EC000, length = 0x000080 /* on-chip FLASH for _c_int00 */
DRVLIB : origin = 0x3EC080, length = 0x000500
FLASHC : origin = 0x3EC580, length = 0x003A80 /* on-chip FLASH */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
PAGE 1 :
/* For this example, H0 is split between PAGE 0 and PAGE 1 */
BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */
RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */
DRAMH0 : origin = 0x3FB900, length = 0x000700
}
SECTIONS
{
driverlib :
{
-ldriverlib.lib(.econst)
-ldriverlib.lib(.text)
} > DRVLIB, PAGE = 0
Flash28_API:
{
-lFlash2808_API_V302.lib(.econst)
-lFlash2808_API_V302.lib(.text)
-lbufops.lib(.econst)
-lbufops.lib(.text)
-lstrtol.lib(.econst)
-lstrtol.lib(.text)
} LOAD = FLASHD,
RUN = FLS1_RAML0,
LOAD_START(_Flash28_API_LoadStart),
LOAD_END(_Flash28_API_LoadEnd),
RUN_START(_Flash28_API_RunStart),
PAGE = 0
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
.cinit : > RAMM0 PAGE = 0
.pinit : > RAMM0, PAGE = 0
.text : > PRAMH0 PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs :
{
../DSP280x_CodeStartBranch.obj(.text)
} > RAMM0, PAGE = 0
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > DRAMH0 PAGE = 1
.switch : > RAMM0 PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
// .sysmem : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > DRAMH0, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > PRAMH0 PAGE = 0 /* Math Code */
IQmathTables : > BOOTROM, type = NOLOAD, PAGE = 0
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
There are a number of hacks to pin some sections at the fixed position. It's ugly now.
I'm able to load HEX file via XModem and place it in the memory. Then jump to the new Entry point. I didn't find Xmodem-related API and write it on my own:
https://github.com/ya-mouse/f280x_bufops
Also I use that library to burn HEX file over Xmodem using TI's Flash API.
The problem become in the functions' order for the flashed sections, e.g "driverlib". How can I sort objects and pin a list of available routines that could be reused by the RAM-linked version? Other routines, that are not in the FLASH, should be placed into the memory. I need something like a map of "external" routines that should be used during link stage. Is it possible?
