Hi,
I read http://processors.wiki.ti.com/index.php/Trace_Functionality_And_Capabilities very carefully which included a detailed illustration of the AET logic. For 64x and 64x+ devices, the Wiki article said:
"The 64x and 64x+ devices implemented with AET have a total of 14 trigger builders. Each trigger builder is a member of one of three families, the 7-Wide, 3-Wide, and 1-Wide. Of the 14 trigger builders, 2 are 7-Wide and there are 6 each of the 3-Wide and 1-Wide."
In the following paragraph it also said:
"Each trigger builder is hard wired to a specific set of events. So, in order to generate a Halt CPU trigger, a Trigger Builder that can generate a Halt CPU trigger must be selected. The user doesn't need to be aware of which trigger builders are connected to which events, as UBM or AETLIB will take care of that for them. However, it's convenient to understand that trigger builders are limited resources and there can potentially be conflicts if multiple jobs need to use the same trigger builder."
WWhereas these two paragraphs are discussed in the paragraph for C64x & C64x's AET, this question also extends to devices without AET. Essentially as the Wiki article has explained:
- AET is for triggering, what it triggers can either be halt, trace, AINT, or counter
- trace is for logging, which can either be internally via ETB or externally to emulator via a Trace pod
Therefore for ARM cores (OMAP L138's ARM926EJ-S) without AET, I wonder whether the Wiki article still apply? Is that at one time there is only one trace job allowed? Does UBM still smart enough to recognized potential conflicts?
Paul
