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Incorrect disassembly for ARM floating point compare instruction in CCS 5.3

Chester Gillon
Guru 92251 points

CCS 5.3.0.00090 is showing me the following diassembly for a LM4F120H5QR target:

          sqrtf:
00004928:   EEB50AC0 FCMPEZS         S0, S0
0000492c:   B508     PUSH            {R3, LR}
0000492e:   EEF1FA10 FMXR            PC, FPSCR
00004932:   D206     BCS             $C$L1
00004934:   2001     MOV             R0, #0x1
00004936:   F7FFFE2F BL              _Feraise
0000493a:   4803     LDR             R0, $C$CON1
0000493c:   ED900A00 FLDS            S0, [R0, #0]
00004940:   BD08     POP             {R3, PC}
          $C$L1:
00004942:   EEB10AC0 FSQRTS          S0, S0
00004946:   BD08     POP             {R3, PC}

For the first instruction EEB50AC0 according to the ARM®v7-M Architecture Reference Manual I would have expected the disassembled instruction to be:

FCMPEZS         S0, 0.0

Rather than the following which is disassembled by CCS 5.3:
FCMPEZS         S0, S0
Based upon the source code for the sqrtf function from the TI ARM compiler 5.0.5 RTS I expect the first instruction to a comparing S0 against zero, rather than what the CCS diassembly is showing as a compare of S0 against S0.

Under the CCS Project Properties -> Debug -> Cortex M3 Disassembly Style the default of "Mixed ARM/Thumb" is selected.

On a related note, is it possible to get the CCS ARM diassembly to list the Unified Assembler Language (UAL) mnemonics, rather than the "legacy" mnemonics?

  • 0
    TI__Guru**** 466071 points

    Hi Chester,

    Thank you for reporting this issue.

    Chester Gillon said:

    For the first instruction EEB50AC0 according to the ARM®v7-M Architecture Reference Manual I would have expected the disassembled instruction to be:

    FCMPEZS         S0, 0.0

    [/quote]

    Sorry, noob question, but I'm hardly an ARM expert so could you point out where in the Manual you were able to discern that the opcode translated to that assembly instruction? Thanks

    ki

  • 0 in reply to Ki
    TI__Guru**** 466071 points

    I've filed a bug for the first issue you reported. The tracking ID is: SDSCM00047725

    Thanks

    ki

  • 0 in reply to Ki
    Guru 92251 points

    Ki-Soo Lee said:
    Sorry, noob question, but I'm hardly an ARM expert so could you point out where in the Manual you were able to discern that the opcode translated to that assembly instruction?

    I was looking at ARM®v7-M Architecture Reference Manual, ARM ID ARM DDI 0403Derrata 2010_Q3 (ID100710) downloaded from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html. Section A7.7.222 VCMP, VCMPE gives the instruction encoding for floating point compare instructions in question.

    One complication is that the main body of the ARM®v7-M Architecture Reference Manual uses the Unified Assembler Language (UAL) mnemonics, whereas the CCS disassembly is using the "legacy" pre-UAL mnemonics. Therefore, I also had to refer to section B.3 Pre-UAL floating-point instruction mnemonics, which gives the mapping between the UAL and pre-UAL mnemonics.

    [The TI LM4F documentation doesn't list the ARM instruction encoding. To obtain the instruction encoding in the ARM®v7-M Architecture Reference Manual you have to register with ARM and agree to their license terms]

  • 0 in reply to Chester Gillon
    TI__Intellectual 2010 points

    I don't see this issue when using the disassembler from either the 5.1.x or 5.0.x compiler toolset.  The issue should go away if you upgrade the compiler tools.

    -Mack

  • 0 in reply to mjoyner
    Guru 92251 points

    mjoyner said:
    I don't see this issue when using the disassembler from either the 5.1.x or 5.0.x compiler toolset.  The issue should go away if you upgrade the compiler tools.

    I was originally using TI ARM compiler v5.0.5 when the problem was seen.

    Based upon other threads I have seen think that CCS uses it's own disassembler when debugging, rather than the same disassembler as the compiler tool chain. Therefore, CCS may produce a different disassembly to the compiler tool chain.

  • 0 in reply to Chester Gillon
    TI__Intellectual 2010 points

    Do you see this same issue with CCS 5.4?

    -Mack

  • 0 in reply to mjoyner
    Guru 92251 points

    mjoyner said:
    Do you see this same issue with CCS 5.4?

    Yes, just checked with CCS 5.4.0.00091 (and TI ARM compiler v5.1.1)

  • 0 in reply to Chester Gillon
    TI__Intellectual 2010 points

    Can you tell me what exact steps you took after installing CCS 5.4 to see the issue?  I'm still not able to recreate the problem.

  • 0 in reply to mjoyner
    TI__Intellectual 2010 points

    I am finally able to reproduce the issue.  Thanks.