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Using different FTDI chip (FT4232H) as on-board emulator - possible?



Hi,

The XDS100v2 JTAG emulator (and the on-board emulator of the ICE dev kit) are based on the FTDI FT2232 chip.
However, FTDI has a newer FT4232H chip (having more channels). Is that possible to use it as onboard emulator?

1. Except for VID/PID configuration, is there any TI specific firmware/CPLD image downloaded into the FT2232 chip or only FTDI supplied (by default) code is used?

2. There are some pins connected to FTDI GPIO (EMU0/1, SysReset), what defines the mapping of these on PC side? Can this mapping be altered?

Best,
Vasili

  • Hi,

    The FT232 chip is supposed to be just a serial converter. I don't think any TI specified firmware should be present. 

    Regards,

    Gautam

  • Yeah, I suppose so. But I would be glad to hear it from TI. Besides, for using it I need the second answer too.

  • Sure sure. I would recommend the same too. 

    Regards,

    Gautam

  • Vasili,

    The FT4232 is very similar to the original, therefore this seems to indicate the changes can be very minimal: FTDI programming (VID/PID and some strings) and maybe (and a big maybe) the companion CPLD could be left intact if using a similar pinout - obviously changes to the PCB are required to accommodate the new device.

    However, this device probably uses a different set of FTDI device drivers and I am not 100% sure if Code Composer Studio will recognize it.

    Since you are exploring an untested design, we can't provide any guidelines and support other than what is provided by the XDS100 design file package (check section 5 of the XDS100 page).

    Regards,

    Rafael

  • Hi,

    1. As far as I know the FTDI drivers are the same for both devices (though this doesn't mean CCS will recognize them).

    2. Now, I'm confused. As I see from the XDS100v2 schematics it has CPLD in addition to FTDI. On the other hand, the on-board emulator on ICE board doesn't have any CPLD. So what is this CPLD needed for?

    Regards,
    Vasili

  • Vasili,

    2. The CPLD performs some housekeeping functions, including signal isolation during transitions (resets, for example). I had trouble with these things in the past in some Sitara development boards and therefore I personally would stay true to the original design (you don't want to risk finding out unexpected problems with production boards).

    Cheers,

    Rafael

  • I see. Thanks for the warning!
    But in our case, we want to leave onboard JTAG just as a backup option for programming if something got corrupted. We can't allow ourselves to put yet another CPLD chip just for that... The ICE dev kit proves that it conceptually works without the CPLD. Given we design it as rarely used backup, we'll take the chance...

    Anyway, some JTAG signals (e.g. TDI, TDO, TMS) in XDS100v2 are connected to dedicated FTDI pins (according to FTDI datasheet these pins reserved for these functions). But some other pins (e.g. EMU0/1, and SysReset) are connected to pins marked as GPIO in FTDI datasheet. Is the mapping of these signals on GPIO pins hardcoded in the JTAG PC side driver or can be altered in some text file?
    In other words if SRESET is connected t0 ACBUS0 pin, but if I move it to, say, ADBUS5 pin, can I alter the PC to work or that requires recompiling the JTAG driver which is closed source?

    Regards,
    Vasili